At low frequencies (<50 MHz), the signals remain within the data characterization limits, and the circuit board performs as intended. When speed increases impedance mismatching, crosstalk, reflections, ringing, and ground bounce issues are seen due to the effects of higher frequencies. These factors not only affect the digital properties but also the analog properties of the system. These issues are commonly noticed these days due to the increasing data rates for I/O and memory interfaces. Practically, these problems can be avoided by implementing high-speed layout design rules or by employing state-of-the-art PCB design services.
What is a high-speed signal?
Signals with frequencies above 50 MHz are considered high-speed signals (clock signals). Ideally, a clock signal is a square wave, but it is practically impossible to change its ‘LOW’ level to a ‘HIGH’ level (and vice versa), instantly. It has a specific rise and fall time due to which it appears to be a trapezoid in the time domain. It is worth noticing that the amplitude of the higher frequency harmonics of the clock signal in the frequency domain depends upon its rise and fall time. If the rise time is longer, the magnitude of the harmonics will become smaller.
What are the high-speed layout design rules?
While designing a circuit board for high-speed applications, strongly focus on the layout. The layout design rules mentioned below will not only fulfill the design requisites but will also reduce the manufacturing cost.
1. Place a common ground plane below the signal traces.
This ensures minimal impedance between any two ground points in the board. The ground plane should never be broken by routing any tracks in it.
When there is a requirement to route tracks on both sides of a circuit board in the same area, a good ground plane is no longer guaranteed. In this case, the only solution is to implement ground planes on both sides of the traces that are interconnected by plenty of vias.
2. Via placement.
Improper positioning of vias can create plane areas in which vias block the flow of current or narrow the copper spaces which could result in high current density resulting in voltage drop. It is better to place vias forming a grid, it leaves enough space between the vias to incorporate the power plane (place them 15 mils apart).
3. Place the vias symmetrically to eliminate impedance discontinuities.
4. Maintain minimum bends while routing.
If the bends are required, then 135° bends should be implemented instead of 90° as shown in the figure (right side).
5. Add serpentine traces to achieve a specific trace length.
6. Maintain at least 3W spacing between the signal traces to minimize crosstalk.
7. Implement daisy chain routing to avoid long stubs.
The long stub traces may act as antennas and consequently increase problems with EMC standards compliance.
8. Avoid placing components and vias between differential pairs.
It helps to mitigate impedance discontinuities and EMI issues.
9. Route the differential pairs symmetrically and keep the signals in parallel.
10. When routing a differential pair, both traces should be routed on the same layer.
It ensures the achievement of the impedance requirements.
11. Implement length matching using serpentines to maintain the time of arrival at a destination (clock skew) between different traces and pairs of signals.
12. Place the serpentine traces at the point of length mismatch.
This ensures that the positive and negative signal components are propagated synchronously over the connection.
13. Add compensation close to the bend with a maximum distance of 15 mm.
14. The mismatches in each segment of a differential pair connection should be matched individually.
Vias are used to separate the differential pair into two segments. It enables synchronous propagation of the positive and negative signals through the vias.
In high-speed layout designs, signal integrity and EMC regulation implementation play a significant role.
