Avoiding signal integrity issues in a PCB is an extremely complex task for designers. It requires a deep understanding of signal integrity design rules and techniques. With the introduction of faster logic families, the designers have realized that simple PCB layouts cannot survive the signal integrity requirements.
The high-speed designs come with peculiar signal integrity issues that can give you a headache if not treated properly. Engineers are always advised to consider certain best PCB design services to minimize signal integrity issues in the early design cycle so that expensive design iterations can be avoided.
As we proceed, we will be providing more insight on the following topics:
- What is signal integrity in a PCB?
- Need for signal integrity in a PCB
- 9 factors that lead to signal integrity issues in a PCB
What is signal integrity in a PCB?
Signal Integrity (SI) signifies the signal’s ability to propagate without distortion. Signal integrity is nothing but the quality of the signal passing through a transmission line. It gives the measurement of the amount of signal degradation when the signal travels from the driver to the receiver. This problem is not a major concern at lower frequencies but is an important factor to consider when a PCB operates at a higher speed and a high-frequency (> 50MHz). In the high-frequency regime, both digital and analog aspects of the signal need to be taken care of.
When a signal propagates from the driver to the receiver, it doesn’t remain the same, whatever has been sent originally will be received with varying degrees of distortion. This signal distortion happens due to factors like impedance mismatch, reflections, ringing, crosstalk, jitter, and ground bounce. A designer’s primary aim should be minimizing such factors so that the original signal could make it to the destination with minimum distortion. Special care is also needed to maintain signal quality and to control their undesirable effects in electronic circuitry. Read our post on controlled impedance routing using Altium.
Need for signal integrity in a PCB
When we have signal integrity issues in a PCB, it may not work as desired. It may work in an unreliable manner – works sometimes and sometimes not. It may work in the prototype stage, but often fail in volume production; it may work in the lab, but no reliably in the field; it worked in older production lots, but fails in new production lots, etc. A signal is said to have lost its integrity when:
- It gets distorted, i.e. its shape changes from the desired shape
- Unwanted electrical noise gets superimposed on the signal degrading its signal to noise (S/N) ratio
- It creates unwanted noise for other signals and circuits on the board
A PCB is said to have requisite signal integrity when:
- All signals within it propagate without distortion
- Its devices and interconnections are not susceptible to extraneous electrical noise and Electromagnetic Interference (EMI) from other electrical products in its vicinity as per or better than regulatory standards
- It does not generate or introduce or radiate EMI in other electrical circuits/cables/ products either connected to it or in its vicinity, as per or better than regulatory standards
High-Speed PCB Design Guide8 Chapters - 115 Pages - 150 Minute Read
- Explanations of signal integrity issues
- Understanding transmission lines and controlled impedance
- Selection process of high-speed PCB materials
- High-speed layout guidelines
9 factors that lead to signal integrity issues in a PCB
Perhaps the most important cause of signal integrity issues in a PCB is faster signal rise times. When circuits and devices are operating at low-to-moderate frequencies with moderate rise and fall times, signal integrity problems due to PCB design are rarely an issue. However, when we are operating at high (RF & higher) frequencies, with much shorter signal rise times, signal integrity due to PCB design becomes a very big issue.
Factors that contribute to signal integrity degradation in a PCB:
Generally speaking, fast signal rise times and high-signal frequencies increase signal integrity issues. For analytical purposes, we can divide various signal integrity issues into the following categories:
1. Signal degradation due to uncontrolled line impedances
Signal quality on a net depends on the characteristics of the signal trace and its return path. During travel on the line, if the signal encounters changes or nonuniformity in the impedance of the line, it will suffer reflections that cause ringing and signal distortion.
Moreover, the faster the signal rise time, the greater will be the signal distortion caused by changes in uncontrolled line impedances. We can minimize signal distortion due to reflections by reducing or eliminating line impedances changes by:
- Ensuring that signal lines and their return paths act as uniform transmission lines having uniform controlled impedances.
- Having signal return paths as uniform planes placed close to signal layers.
- Ensuring that controlled impedance signal lines see matched source impedances and receiver impedances – same as the characteristic impedance of the signal line. This may call for the addition of proper terminating resistors at the source and receiver ends.
2. Signal degradation due to other impedance discontinuities
As we mentioned earlier, if the signal encounters a discontinuity in impedance during its travel, it will suffer reflections that cause ringing and signal distortion. Discontinuities in the line’s impedance will occur at the point of encountering one of the following situations:
- When a signal encounters a via in its path.
- When a signal branches out into two or more lines.
- When a signal return path plane encounters a discontinuity, like a split in the plane when line stubs are connected to signal lines.
- When line stubs are connected to signal lines.
- When a signal line starts at the source end.
- When a signal line terminates at the receiver end.
- When signal and return paths are connected to connector pins.
And, the faster the signal rise time, the greater will be the signal distortion caused by impedance discontinuities. We can minimize signal distortion due to line impedance discontinuities by:
- Minimizing the effects of discontinuities caused by vias and via stubs by using smaller microvias and HDI PCB technology.
- Reducing trace stubs lengths.
- Routing traces in daisy chain fashion rather than multi-drop branches when a signal is used at more than one place.
- Proper terminating resistors at the source and receiver ends.
- Using differential signaling and tightly coupled differential pairs, which are inherently more immune to discontinuities in signal return path planes.
- Ensuring that at connectors where discontinuity occurs, signal lines are made as short and signal return paths as wide as possible.
3. Signal degradation due to propagation delay
Signals take finite times as they travel on a PCB from source to receiver. The signal delays are proportional directly to signal line lengths and inversely proportional to signal speed on the specific PCB layers. If data signals and clock signals do not match overall delays, they would arrive at different times for detection at the receiver, and this would cause signal skews; and excessive skew would cause signal sampling errors. As signal speeds become higher, the sampling rates are also higher, and allowable skew gets smaller, causing a greater propensity for errors due to skew.
TIP: Skew in a group of signal lines can be minimized by signal delay matching, primarily by trace length matching.
4. Signal degradation due to signal attenuation
Signals suffer attenuation as they propagate over PCB lines due to losses caused by conducting trace resistances (which increases at higher frequencies due to skin effect) and dielectric material dissipation factor Df. Both these losses increase as frequency increases, therefore higher frequency components of signals will suffer greater attenuation than do the lower frequency components; this causes a reduction in signal bandwidth, which then leads to signal distortion by the increase in signal rise time; and excessive signal rise time increase results in errors in data detection.
TIP: When signal attenuation is an important consideration, one has to choose the right type of low loss high-speed material and proper control over trace geometries to minimize signal losses.
5. Signal degradation due to crosstalk noise
A fast voltage or current transition on a signal line or return path plane may couple onto adjacent signal lines causing unwanted signals called crosstalk and switching noise on the adjacent signal lines. The coupling occurs due to mutual capacitance and mutual inductance between the traces. This mutual capacitive and inductive coupling can be reduced by increasing the space between the traces. As a thumb rule, space should be three times the trace width (3W). And as always, faster rise time signals create more crosstalk and switching noise.
Crosstalk and switching noise can be reduced by:
- Increasing the separation between adjacent signal traces.
- Making the signal return paths as wide as possible, and uniform like uniform planes, and avoiding split return paths.
- Using a lower dielectric constant PCB material.
- Using differential signaling and tightly coupled differential pairs, which are inherently more immune to crosstalk.
6. Signal degradation due to power and ground distribution network
Power and ground rails or paths or planes have very low, but FINITE nonzero impedances. When output signals and internal gates switch states, currents through power and ground rails/paths/planes change, causing a voltage drop in power and ground paths. This will decrease the voltage across the power and ground pins of the devices. The higher the frequency of such instances, and faster the signal transition times, and the higher the number of lines switching states simultaneously, the greater is the voltage decrease across power and ground rails. This will reduce signals’ noise margins, and if excessive, would cause devices to malfunction.
To reduce these effects, the power distribution network has to be so designed as to minimize the power system’s impedance:
- Power and ground planes should be placed as close together and as near to the PCB surface as possible. This will reduce via inductances.
- Multiple low inductance decoupling capacitors should be used across power and ground rails and they should be placed as close to device power and ground pins as possible.
- Use device packages with short leads.
- The use of thin high-capacitive cores for power and ground considerably increases the capacitance and reduces impedance between power and ground rails. Read how we can reduce parasitic capacitance in PCB layout.
7. Signal degradation due to EMI/EMC
EMI/EMC increases with frequency and faster signal rise times. Radiation far-field strength increases linearly with frequency for single-ended signal currents, and squarely with differential signal currents. Read PCB design guidelines for EMI and EMC for a detailed explanation.
TIP: EMI can also be reduced by reducing the current loop area.
Signal Integrity eBook3 Chapters - 12 Pages - 20 Minute Read
- Impedance discontinuities
- Reflections, ringing, overshoot and undershoot
- Via stubs
8. Signal integrity issues due to via stub and trace stub
A via stub is the part of a via which is not used for signal transmission. A via stub acts as a resonant circuit with a specific resonant frequency at which it stores maximum energy within it. If the signal has a significant component at or near that frequency, that component of the signal will be heavily attenuated due to the energy demands of the via stub at its resonant frequency. In the example depicted below, part A of the via is used for signal propagation from the conductor C1 on an outer layer to the conductor Cn on an inner layer. But the part B of the via is extraneous – thus, is the via stub. Learn more about Via Stubs and Their Effects on Signal Attenuation and Data Transfer Rates here.
The long stub traces may act as antennas and consequently increase problems to comply with EMC standards. Stub traces can also create reflections that negatively affect signal integrity. Pull-up or pull-down resistors on high-speed signals are common sources of stubs. If such resistors are required then route the signals as a daisy chain.
9. Signal integrity issues due to ground bounce
Due to excessive current drawn the circuit’s ground reference level shifts from the original. This is due to ground resistance and interconnect resistance such as bonding wires and traces. The ground voltage levels at different points in the ground will, therefore, be different. This is known as a ground bounce as ground voltage will vary with the current.
Techniques for decreasing ground bounce:
- Implement decoupling capacitors to local ground.
- Incorporate serially-connected current-limiting resistors.
- Place decoupling capacitors close to the pins.
- Run proper ground.
The signal’s rise time is a critical parameter in SI issues. To attain a desired signal integrity level, we should focus on impedance control, attenuation, ground bounce, propagation delay, and EMI/EMC. Signal integrity measures should be adopted during the design phase of a PCB because we cannot afford to come up with a new design every now and then. It is better to treat it beforehand rather than let it ruin your device’s performance in real-time. Check this post on How to Achieve a Robust PCB Design Workflow for Signal Integrity? to gather more information on PCB designing for signal integrity.
PCB Transmission Line eBook5 Chapters - 20 Pages - 25 Minute Read
- What is a PCB transmission line
- Signal speed and propagation delay
- Critical length, controlled impedance and rise/fall time
- Analyzing a PCB transmission line