Power Distribution Network Analyzer

The PDN Analyzer uses a correct-by-construction approach to model impedance behavior across the entire frequency spectrum of your power delivery network.

The tool calculates the target impedance, checks whether each stage of the PDN meets its impedance requirements, auto-selects a suitable capacitor (with MPNs), and plots the impedance profile.

It also helps you analyze:

1. Voltage regulator module (VRM) suitability for low-frequency power delivery
2. Bulk and decoupling capacitor requirements
3. Parasitic effects on PDN

Key features of the PDN Analyzer

• Calculates the target impedance based on voltage, current, and ripple specifications.
• Validates VRM performance at low frequencies to ensure that your regulator can maintain the target impedance without relying on downstream capacitance.
• Automatically selects the right bulk and decoupling capacitor values.
• Computes parasitic contributions from plane capacitance, capacitor via loops, current spreading inductance, and BGA via inductance.
• Plots the complete PDN impedance profile across the full frequency spectrum and compares it with your target impedance in real time.
• Verifies the charge adequacy of the combined capacitor network against the minimum charge required to sustain transient current demand.

How to use the Power Distribution Network Analyzer

The tool is organized into 9 sections for configuring and validating your PDN.

Follow the steps below in the same sequence.

Section 1: Target Impedance

This section determines the target impedance requirements for your design.

Step 1: Enter Vcc (V), Vcc ripple (%), Imax (A). From the Select input parameter dropdown, choose either Signal Frequency or Rise Time and enter the corresponding value (MHz or ns).

Step 2: Click Calculate.

Based on the input parameter, the tool computes the Highest Signal Frequency (Fm) (MHz) or Signal Rise Time (tr) (ns) and calculates the Target Impedance (Ztpdn) (Ω).

This section establishes the maximum allowable impedance for your PDN and serves as the reference for all subsequent calculations.

Section 2: Select Right Voltage Regulator Module (VRM)

This step verifies whether the chosen VRM can support the target impedance requirements at low frequencies. The regulator’s impedance should be less than the target impedance.

Step 1: Enter Internal Resistance (Ω) and Internal Inductance (nH).

Step 2: Click Calculate. The tool determines VRM Actual Impedance (Zact) (Ω)

If the VRM impedance exceeds the target limit, the tool shows a High Impedance warning. Otherwise, it displays Good, as shown below.

Section 3: Bulk Capacitance

This section determines the requirements for bulk capacitors, which take over when the VRM becomes inductive at mid-frequencies.

Step 1: Click Calculate.

The tool computes:

• F_bulk low (KHz) (Lower frequency limit for bulk capacitors)
• F_bulk high (MHz) (Upper frequency limit for bulk capacitors)
• New F_bulk high (MHz) (Adjusted high frequency after optimization)
• Req C total (µF) (Total bulk capacitance required)
• Target ESR total (mΩ) (Desired equivalent series resistance of bulk capacitors)
• Max ESL total (nH) (Maximum allowable equivalent series inductance for bulk capacitors)
• Min SRF (MHz) (Minimum self-resonant frequency)
• Min V (volts) (Minimum voltage rating for capacitors)

Step 2: Choose the required capacitor values. You can let the tool auto-select them or add them manually.

• Case 1: Click Auto Select to populate the required capacitor values.

• Case 2: Click Manual Select to browse and add capacitors from the Bulk Capacitance Library.

• • Select the respective +Add button to populate the capacitor, then close the dialog box.

• The chosen capacitor will then be displayed below.

Section 4: Plane Capacitance

This step calculates the natural capacitance contributed by the dielectric between the power and ground planes.

Step 1: Enter Length (inches), Width (inches), Height b/w Power & Gnd (mils), and Dielectric (εr).

Step 2: Click Calculate.

The tool computes Plane Capacitance (nF). This value feeds into the overall impedance model as a passive contribution from your stack-up to the PDN before any discrete capacitors are added.

Section 5: Capacitor Via Loop Inductance

This calculation determines the parasitic mounting inductance introduced by the vias connecting each decoupling capacitor.

Step 1: Enter Via Height (mils), Via Pitch (mils), and Via Diameter (mils).

Step 2: Click Calculate.

The tool displays Mounting Inductance (nH).

This inductance is associated with each decoupling capacitor in the PDN. Lower mounting inductance improves high-frequency decoupling effectiveness.

Section 6: Spreading Loop Inductance

This section determines the current spreading inductance for a single via pair. The tool divides this value by the total quantity of capacitors in the network.

Step 1: Enter Via Diameter (mils), Height (mils), and Pitch (mils).

Step 2: Click Calculate.

The tool displays Single Pair inductance (nH).

This inductance represents the current spreading between the power and ground planes and is incorporated into the overall PDN impedance model.

Section 7: BGA Via Loop Inductance

This section calculates the parasitic inductance specific to the vias associated with the BGA packages.

Step 1: Enter BGA Via Height (mils), BGA Via Pitch (mils), BGA Via Diameter (mils), and Parallel Pairs.

Step 2: Click Calculate.

The tool shows BGA Inductance (nH). This inductance directly influences high-frequency current delivery at the device power pins and is included in the overall PDN model.

Section 8: Decoupling Capacitance

This step determines the high-frequency capacitor requirements needed to maintain the target impedance.

Step 1: Click Calculate.

The tool computes:

• F_decap low (MHz) (Lower frequency for ceramic caps)
• F_decap high (Fm) (MHz) (Upper frequency limit)
• New F_decap high (MHz) (Adjusted frequency)
• Req C total µF (Required capacitance)
• Target ESR total (mΩ) (Target Equivalent Series Resistance of decoupling capacitors)
• Max ESL total (nH) (Maximum equivalent series inductance of decoupling capacitors)
• Min SRF (MHz) (Minimum self-resonant frequency of decoupling capacitors)
• Min V (volts) (Voltage rating of decoupling capacitors)

These values define the capacitor requirements needed to maintain the target impedance at high frequencies.

Step 2: Choose the required capacitor values. You can let the tool auto-select them or add them manually.

• Case 1: Click Auto Select to populate the required capacitor values.

• Case 2: Click Manual Select to browse and add capacitors from the Decoupling Capacitance Library.

• • Select the respective +Add button to include the capacitor in your design, then close the dialog box.

• The chosen capacitor will then be displayed below.

Section 9: Quick Charge Check

In the final section, you can verify whether the selected network can supply the required charge during transient events.

Step 1: Click Verify.

The tool compares Min Required C (µF) and Total C (µF).

The result is displayed as either PASS (green) or LOW (red) as shown below.

How to interpret the impedance response graph

The right panel plots your PDN impedance across the entire frequency range. The graph displays what each component group contributes and where the impedance breaks down without them.

Here are the parameters defined in the graph:

• Target Z: The maximum allowable impedance.
• Fm: The highest frequency of interest at which the power distribution rail is designed to effectively deliver power.
• VRM Only: Impedance contribution of the voltage regulator module alone.
• VRM + Bulk: Impedance response after adding the bulk capacitors.
• VRM + Bulk + Plane: Capacitance contribution by the PCB power and ground planes.
• VRM + Bulk + Plane + Series Ind: Contribution of mounting, spreading, and package inductance to the impedance profile.
• PCB Level PDN (No Series Ind): PCB-level power distribution network without the influence of series inductance.
• Final System PDN (With Series Ind): The complete PDN, including the VRM, capacitors, PCB capacitance, and parasitic inductances. This value should remain below the target impedance limit across the frequency range of interest.

Evaluating the results:

A successful PDN design keeps the Final System PDN impedance below the Target Z.

Impedance peaks indicate resonance caused by interactions between capacitors and parasitic inductances. If the final system PDN impedance exceeds the target Z, select a suitable capacitor and update the graph.

Graph controls

• Legend toggles: Click on the respective parameter name to show or hide individual curves.
• Download PNG: Saves a high-resolution image of the graph.
• X Min/X Max: Frequency range on the graph.
• Y Min/Y Max: Impedance range on the graph.
• Apply View: Updates the graph using the specified axis limits.
• Reset View: Restores the default graph view.
• Update Graph: Refreshes the graph using the latest design inputs.

The Power Distribution Network Analyzer evaluates and optimizes the PDN by combining target impedance calculations, parasitic modeling, and intelligent capacitor selection.

Use this tool to build a compliant power network, validate power integrity, and improve overall system reliability.