How to Design PCBs for Data Centers and AI Servers

Designing PCBs for AI servers and hyperscale data center platforms requires architectures that support extreme routing density, high-speed serializer/deserializer (SerDes) signaling, and low impedance power delivery.

Layout engineers and signal integrity experts must adopt HDI for fine-pitch BGAs and select materials that meet the loss budgets of 112G and emerging 224G PAM4 signaling for high-performance computing systems.

In this article, you’ll learn printed board types used in hyperscale facilities, how to pick materials for 112G/224G signaling, and stack-up and layout techniques for long-term reliability.

Highlights:

1. Use HDI in data center PCBs when BGA pitch ≤0.5 mm or the routing density exceeds the through-hole breakout capability.
2. Design graphics processing unit (GPU) power delivery using multi-phase voltage regulators, low-inductance vias, and strong decoupling to handle sudden high current demands.
3. Select very-low-loss or ultra-low-loss laminates (D_f ≤0.004) for 112G/224G PAM4 channels, and reserve modified FR4 for non-critical layers.
4. Use low-profile copper to minimize insertion loss at multi-GHz frequencies.

Data center hierarchical model

Modern servers deploy thousands of systems organized into racks and clusters. Each rack typically contains multiple high-performance processors connected through high-speed switch fabrics.

This infrastructure follows a hierarchical model, progressing from the facility level to clusters, racks, server nodes, and ultimately their underlying circuit boards.

Inside each server node, multiple boards work together to support compute, networking, storage, and power delivery functions. These subsystems are discussed in detail in later sections.

This model is widely deployed across major data center campuses in the United States, including Ashburn (Northern Virginia), Santa Clara (Silicon Valley), Dallas, Phoenix, and Atlanta.

Additional hyperscale campuses supporting global cloud and AI infrastructure are located in Quincy, Prineville, and Council Bluffs. These sites host massive server clusters operated by cloud providers such as Microsoft, Google, and Meta.

Amazon Web Services operates large campuses in Northern Virginia, Oregon, and Ohio.

Thousands of high-performance systems and network switches run continuously to support global cloud platforms and large-scale AI workloads.

What are the main challenges in high-speed boards for servers?

Higher network bandwidth requires faster SerDes signaling, which tightens board design margins and places stringent demands on signal integrity, materials, and manufacturing.

Modern systems operate at 112G and emerging 224G SerDes, where each lane carries 112 Gb/s and 224 Gb/s of data, respectively, using PAM4 modulation.

As networks evolve to support AI clusters and large-scale cloud workloads, each new Ethernet generation increases switch throughput while pushing signaling speeds higher. This is summarized in the table below.

These higher data rates introduce several key challenges in maintaining signal integrity, material performance, and manufacturing feasibility.

1. Signal integrity constraints at 112G/224G data rates: At these speeds, circuit board channels are highly sensitive to loss and discontinuities. Factors such as dielectric loss, copper surface roughness, and via stubs significantly degrade signal quality and reduce channel margin.

   

Maintaining signal integrity, therefore, requires controlled impedance routing, minimized discontinuities, and optimized via structures.

2. Material and stack-up limitations at multi-GHz frequencies: At high frequencies, board material properties become a dominant factor in channel performance. Standard FR4 materials are often too lossy, requiring the use of very-low-loss or ultra-low-loss laminates for high-speed layers.

Designers must also carefully engineer stack-ups to balance signal integrity, power delivery, and manufacturability, often using hybrid material strategies to control cost.

3. Manufacturing challenges in high-speed, high-density boards: Higher electrical performance requirements in hyperscale boards push the limits of fabrication. Important constraints include microvia aspect ratio limits (typically 0.8:1), the need for multiple sequential lamination cycles in HDI designs, the use of very-low-profile copper to reduce loss, and tight back-drilling tolerances to eliminate via stubs.

To address these constraints, designs should prioritize manufacturing simplicity by using the least complex HDI structure that meets routing and signal integrity requirements. Close collaboration with fabrication partners is essential to ensure manufacturability.

Sierra Circuits utilizes self-learning automated scaling software (XACT) to ensure precision in HDI stack-up design. The system analyzes material type, thickness, and copper weight on each layer to accurately predict and compensate for material shrinkage.

Visit HDI PCB capabilities to learn more.

What are the commonly used PCBs in data center infrastructure?

Data center systems are organized into compute and accelerator trays that integrate multiple boards. These include server motherboards, network switch boards, storage controllers, backplanes, and power distribution boards, each optimized for compute, connectivity, storage, or power delivery functions.

These board types are discussed in detail in the following sections.

What is a GPU accelerator board?

It is a dedicated add-in card used in AI servers to provide high-performance compute acceleration.

In artificial intelligence systems, GPUs are typically installed on accelerator cards that plug into the server motherboard through high-speed PCB interfaces. Each accelerator card contains a dedicated board designed to support extremely high compute density, large memory bandwidth, and high current delivery.

A typical GPU accelerator board features:

1. GPU processors: The primary compute device responsible for executing AI workloads. These devices are typically packaged in large BGA packages containing thousands of solder balls.
2.  Graphics double data rate (GDDR) or high-bandwidth memory (HBM): Memory devices positioned close to the GPU processor to provide extremely high data transfer rates.
3. Power delivery circuits: Multi-phase voltage regulator modules (VRMs) that supply stable power to the GPU core and memory subsystems.
4. High-speed communication interfaces: PCIe or proprietary interconnects that allow the GPU to communicate with CPUs, networking devices, and other accelerators.

   

5. Thermal management components: Cooling systems such as heat sinks, vapor chambers, and airflow structures designed to dissipate large amounts of heat.

   

GPU circuit boards integrate high-speed signals, high-current power delivery, and advanced circuit board thermal management in a compact form factor.

AI server boards vs. network switch PCBs

Server motherboards are optimized for compute density, high-bandwidth memory interfaces, and high-current power delivery, while switch boards are designed for ultra-high-speed SerDes signaling and channel loss control. These boards operate within the same hyperscale infrastructure, but their printed board design priorities differ significantly.

The table below summarizes the key design differences between the two platforms.

Although both platforms often require HDI stack-ups and low-loss materials, AI server boards are primarily constrained by power density and memory routing, while switch boards are constrained by signal integrity across long high-speed channels.

For high-density layout strategies, download the HDI PCB Design Guide.

HDI PCB Design Guide

5 Chapters - 52 Pages - 60 Minute Read

What's Inside:

• Planning your stack-up and microvia structure
• Choosing the right materials
• Signal integrity and controlled impedance in HDI
• Manufacturing considerations for higher yields

Download Now

What are storage controller boards and NVMe backplane boards?

In data centers, dedicated control boards manage data flow between host processors and storage devices, while backplane boards provide the physical interconnect that links multiple SSDs to the server via PCIe.

Storage systems in hyperscale data centers rely on NVMe backplanes and storage controller boards to connect processors with large arrays of SSDs. These boards route multiple PCIe lanes between host processors, storage controllers, and drive connectors, enabling high-throughput data access across storage clusters.

Unlike GPU accelerator boards that are dominated by compute and power delivery constraints, storage boards are primarily limited by PCIe signal integrity and high connector density. Maintaining reliable PCIe communication across multiple connectors and long routing paths requires careful impedance control and stack-up planning.

Since PCIe channels often traverse multiple connectors and extended printed board traces, you must carefully control impedance, skew, and insertion loss to ensure reliable high-speed data transfer across the storage backplane.

To learn how to integrate connectors to your high-speed designs, watch our webinar: high-speed success at 28-56-112 Gbps with connector-PCB integration.

How to select materials for hyperscale server boards?

Different laminates are assigned to specific layers based on signal speed and performance requirements. This approach allows you to reserve high-performance materials for critical channels while controlling overall manufacturing cost.

As hyperscale data center networks transition to 112G and emerging 224G PAM4 signaling, material selection becomes a vital factor in maintaining channel performance. At these data rates, insertion loss caused by dielectric absorption and copper surface roughness can significantly reduce signal margin across high-speed links.

In many server platforms, hybrid stack-ups combine multiple material types within a single printed board for cost optimization. Critical high-speed (112G or 224G SerDes) layers may use very-low-loss or ultra-low-loss laminates, while other layers use modified FR4 materials for cost efficiency.

When selecting materials for high-speed server boards, designers should also consider additional physical properties such as:

1. Stable dielectric constant (D_k): Target D_k in the range of ~3.0-3.7 with minimal variation across frequency (ΔD_k ≤±0.05–0.1 from 1 GHz to 10+ GHz) to maintain impedance stability.
2. Low dissipation factor (D_f): Use materials with D_f ≤0.0025 to minimize dielectric loss in 112G/224G high-speed channels.
3. High glass transition temperature (Tg): Select materials with T_g ≥170 °C (preferably 180-200°C+) to ensure thermal reliability under sustained workloads.

   

4. Low Z-axis coefficient of thermal expansion (CTE):
   • Below Tg: ≤50 ppm/°C
   • Above Tg: ≤200–250 ppm/°C

This helps prevent via failure during thermal cycling.

5. CAF resistance: Use CAF-resistant laminates to prevent conductive anodic filament failures in high-density multilayer boards. Common materials include Isola Astra MT77, Isola Tachyon 100G, Rogers RO3003, and Rogers RT/Duroid 5880.

Close coordination with the fabricator is essential to confirm laminate availability, thickness tolerances, and resin content before finalizing the stack-up.

At Sierra Circuits, we control curing parameters like temperature, pressure, and time to minimize stress and prevent layer misalignment in hybrid stack-ups.

To learn more, talk to a PCB expert: Book a meeting or call us at +1 (800) 763-7503.

How do circuit board materials affect signal loss in 112G and 224G channels?

Material properties such as dielectric loss, glass weave variation, and copper surface roughness directly impact high-speed channel margin. As signaling rates reach 112G and 224G PAM4, material behavior becomes a dominant factor in channel performance. At these speeds, signal loss is no longer determined solely by routing geometry.

Material selection for 112G and especially 224G systems is typically organized into performance tiers based on dielectric loss characteristics.

Since ULL materials significantly increase circuit board cost, most server platforms use hybrid stack-ups, reserving these laminates for critical SerDes routing layers while using modified FR4 or VLL materials for the remainder of the stack.

PCB DESIGN TOOL

Material Selector

TRY TOOL

Two critical physical attributes in high-speed channels

1. Glass weave skew: Printed board laminates use woven fiberglass cloth embedded in resin. Standard glass styles create alternating bundles of glass fibers and resin pockets, which exhibit different dielectric constants.

When high-speed differential pairs route over these non-uniform regions, one trace may propagate faster than the other, introducing intra-pair skew. At 112G and especially 224G PAM4 signaling rates, even small propagation differences can reduce eye margin.

Common mitigation techniques include:

1. Pick spread-glass laminate styles such as 1067 or 1078. The spread glass creates a uniform dielectric environment and ensures consistent impedance.

   

2. Select prepregs with higher resin content to reduce dielectric variation.
3. Route differential pairs slightly off-angle relative to the glass weave to avoid propagation delays.

These techniques help reduce skew variation across long high-speed channels.

2. Copper surface roughness: At multi-GHz frequencies associated with 112G and 224G signaling, current flow is concentrated within the outer micron of the conductor due to the skin effect. Surface roughness increases the effective conductor path length, which increases insertion loss.

To reduce conductor loss, high-speed server boards typically use very-low-profile copper foils, including:

1. Hyper very low profile (HVLP) copper
2. Very low profile, second-generation (VLP2) or equivalent copper foils

As copper roughness strongly affects high-frequency loss, its parameters must be included in signal integrity simulations and channel modeling to accurately predict insertion loss and channel margin.

Careful control of dielectric loss, glass weave variation, and copper roughness is therefore essential for achieving reliable 224G PAM4 channel performance in next-generation data center platforms.

7 guidelines for designing PCBs for data centers

Modern server platforms integrate large BGA processors, high-speed SerDes channels, and high-current accelerators, all of which impose strict constraints on printed board build-up, routing topology, and component placement.

Follow these design practices to ensure stable electrical performance and long-term reliability in these environments.

1. Define the stack-up based on high-speed channel and PDN requirements

Layer stack architecture directly determines both channel loss behavior and power distribution network (PDN) impedance in hyperscale server boards. At 112G and 224G PAM4 data rates, stack-up planning should occur before schematic capture or routing begins.

Essential stack-up guidelines include:

1. Position high-speed SerDes layers within tightly coupled reference plane pairs to control impedance and suppress mode conversion in multi-GHz channels.
2. Pair power and ground planes to achieve low-inductance PDN structures capable of supporting large transient currents.
3. Maintain symmetrical copper distribution to ensure dimensional stability in a high-layer-count (>20 layers) server board.
4. Use inner layers for high-speed channels where shielding from external noise is strongest.

Utilize field solver tools to verify impedance targets such as 50 Ω single-ended and 100 Ω differential before finalizing dielectric thickness and trace geometries.

PCB DESIGN TOOL

Stackup Designer

TRY TOOL

2. Use HDI for high-speed channel integration and BGA breakout

Modern server processors and GPU accelerators use large BGA packages with thousands of pins, making traditional through-hole breakout techniques insufficient for routing high-speed signals and dense power networks.

At 112G and emerging 224G PAM4 data rates, conventional multilayer structures cannot support the required channel density and via performance. HDI architectures become necessary when breakout density, high-speed channel requirements, or PDN via density exceed the capability of conventional multilayer circuit boards.

In GPU accelerator boards, HDI routing is often required to support HBM interfaces, which operate at extremely high data rates and require strict signal integrity control.

If via-in-pad or stacked microvias are required under the densest BGA regions, HDI becomes mandatory regardless of overall net count.

For more on breakout strategies, see:

• How to breakout a .5 mm BGA
• How to breakout a .4 mm BGA

3. Implement effective electromagnetic containment techniques

High-bandwidth memory interfaces between the GPU and memory devices operate at extremely high data rates and are sensitive to impedance discontinuities, skew, and crosstalk.

To preserve signal integrity, designers should:

1. Route memory channels on dedicated inner layers sandwiched between ground planes.
2. Apply strict length matching and skew control across differential pairs to prevent lane-to-lane misalignment at 112G+ rates.
3. Minimize GPU-to-memory interconnect length to reduce insertion loss and timing uncertainty.
4. Add via stitching grids and ground fences around dense high-speed channel clusters to mitigate electromagnetic interference (EMI).

   

5. Isolate high-current VRM regions from sensitive SerDes and memory interfaces to reduce noise coupling.

For more, download the EMI and EMC Design Guidelines for PCBs.

EMI and EMC Design Guidelines for PCBs

6 Chapters - 77 Pages - 75 Minute Read

What's Inside:

• How electromagnetic interference is generated and spreads
• How to identify EMC requirements and applicable standards
• How to design for electromagnetic resilience
• Common EMI sources: Switching circuits, PWM signals, and motors
• PCB structures that cause radiated emissions
• Practical layout, stack-up, filtering, and shielding guidelines

Download Now

4. Employ a low-impedance power distribution network

Modern GPU accelerators can consume hundreds of watts of power, generating rapid current transients during parallel workload execution. Maintaining stable voltage delivery, therefore, requires a carefully engineered PDN with low impedance across a wide frequency range.

Effective PDN design strategies include:

1. Use multi-phase VRM architectures to support large transient currents from AI workloads.
2. Utilize low-resistance power planes to maintain voltage stability under high GPU current densities.
3. Employ low-inductance via networks to control PDN impedance at high frequencies.
4. Distribute decoupling capacitors between the VRMs and GPU to control PDN impedance during transient load conditions.

   

In high-power accelerator boards, power planes often serve a dual role as thermal spreading layers, helping distribute heat away from the processor while maintaining low electrical impedance.

PCB DESIGN TOOL

Power Distribution Network Analyzer

TRY TOOL

5. Use copper planes and thermal vias for heat spreading

High-power GPU devices generate significant heat, requiring efficient heat transfer through the printed board structure to prevent thermal hotspots.

Accelerator boards, therefore, incorporate several thermal management techniques:

1. Use dense thermal via arrays beneath GPU packages to conduct heat through high-layer-count stack-ups.

   

2. Leverage internal copper planes to spread heat across the circuit board and reduce thermal gradients in high-density regions.
3. Align high-power components with system airflow paths to support effective cooling under sustained workloads.

6. Optimize via structures for 112G and 224G SerDes channels

In high-speed SerDes channels, via structures are a dominant source of signal integrity degradation. Poorly optimized vias can introduce impedance discontinuities and resonant stubs that significantly reduce channel eye margin at gigahertz frequencies.

Unused portions of through-hole vias act as resonant stubs, reflecting energy back into the transmission path and distorting high-speed signals.

To mitigate these effects, you should implement the following strategies:

1. Specify back-drilling to remove unused via barrels, eliminating resonant stubs.
2. Constrain stub lengths below approximately 10 mil, depending on channel frequency.
3. Use microvias or blind/buried vias to eliminate stub formation in fine-pitch BGA breakouts (≤0.5 mm pitch).
4. Validate drill depth tolerances to avoid DFM errors.

7. Design for reliability and long-term server operation

Hyperscale server infrastructure operates continuously for years under high electrical, thermal, and mechanical stress. Printed board materials, mechanical structures, and manufacturing processes must therefore support long-term reliability.

Design considerations include:

1. Reinforce press-fit connector regions to withstand insertion forces.
2. Add mechanical support beneath large heatsinks or heavy components.

Many hyperscale server platforms follow IPC-6012 class 2 benchmarks, while accelerator boards carrying high-value GPUs comply with class 3 standards.

Unlike conventional digital systems, hyperscale server boards must support continuous operation, extreme power density, and multi-GHz signaling while remaining manufacturable at scale.

By applying these high-speed board design practices and aligning stack-up planning, material selection, and HDI strategies early in the design cycle, engineers can achieve reliable 112G/224G operation and ensure scalable, manufacturable AI server boards.

About the technical reviewer:

Dilip Kumar is the Senior Design Manager at Sierra Circuits with over a decade of experience in developing high-speed and HDI PCB designs featuring fine-pitch BGAs. He is proficient in Altium Designer, Cadence Allegro, Eagle PCB, KiCAD, and AutoCAD.

Leading a team of skilled designers and layout engineers, he oversees projects from concept to production, ensuring precision and manufacturability at every stage. Dilip consistently delivers innovative, high-quality designs that meet demanding engineering and business objectives.

Need assistance in building your PCBs? Post your queries on our forum, SierraConnect. Our design and manufacturing experts will help you select one.