6 DFM Issues Designers Should Check Before PCB Manufacturing

by | Apr 14, 2020 | 0 comments

The first checklist we like to implement after receiving Gerber files is signal checks. This checklist holds key parameters that include conductor width, spacing requirements, and hole registration. We would like to shed some light on some of these DFM issues that often arise.

1. Conductor Width

DFM Issues: Conductor Width

Number one on our list of DFM issues is conductor width. Traces on circuit boards connect components to connectors. These traces can be identified as continuous paths of copper that exist on the surface of a PCB. The width of the conductor traces becomes crucial as it directly impacts the functionality of a board. And increasing the signal flow through traces leads to a fair amount of heat. Monitoring trace width also helps to minimize heat build-up that typically occurs on boards. The conductor width also determines the resistance of the traces that directly affect the transmission of a signal.

Many manufacturers opt for their default trace width value available, which may not be suitable for high-frequency applications. Moreover, depending on the application, the trace width is varied, thus affecting the current carrying capacity of the trace. The maximum current carrying capacity for 2 oz copper with temperature rise of 10°C is mentioned in this table.

Maximum Current Capacity (amps)Trace Width (mil)

IPC-2221 gives the formula for calculating the trace width for allowable current:

Width[mils] = A[mils^2]/(Thickness[oz]*1.378[mils/oz])

As per IPC-2221, for internal layers k = 0.024 and for external layers, k = 0.048.

The cross-sectional area A is calculated by below formula:

A[mils^2] = (I[Amps]/(k*(ΔT[deg. C])^ 0.44))^(1/0.725)

Where I is the current, k is a constant, ΔT is temperature rise, and A is the cross-sectional area of the trace.

During the design phase, you should consider the trace width as one of the most important parameters. It is essential to decide the adequate trace width to ensure the performance of the circuit board. This also helps to ensure the safe transmission of current without overheating and damaging the board.

An Impedance and Trace Calculator to Avoid DFM Issues

Check for DFM Issues with the Impedance Calculator

We have developed the online Impedance Calculator tool for calculating the overall value of the minimum trace width. The minimum trace width is determined by the amount of required current and copper weight. We offer thicker conductor traces for higher current requirements. We also offer a thicker copper weight allows for thinner traces.

There are various factors that can affect the selection of the right trace width:

  • Thickness of the copper layer
  • Type of bottom or top layer
  • Length of the track
  • Dielectric height
  • Dielectric constant
  • Inductance and capacitance of the trace
  • Propagation delay

For traces located on the inner layer of the PCB, you should follow special guidelines, such as heat dissipation.

We also understand the need for improvements in signal integrity of the circuit. This has helped us to develop our Impedance Calculator for single-ended and differential pair signals. Furthermore, maintaining a proper signal integrity in the PCB reduces losses such as copper loss and noise.

Having said all of this, we typically suggest our customers to opt for larger traces in order to prevent broken connection, provided there is availability of larger space on the PCB. In your design, try to assign separate D-code for the traces which have to be impedance control.


DFM Handbook

Challenges with Conductor Width

The maximum current carrying capacity of a copper trace usually differs from the theoretical value due to several factors. Some of the factors include number of components, pads and vias. Moreover, large transient surge can lead to the burning down of a trace between pads during initial supply of power or when modifications are implemented on traces. You can consider increasing the trace width to avoid these DFM issues. Solder mask can be applied on PCB traces to avoid transient surge. The solder paste can also be applied on a surface mount technology (SMT) procedure. It is recommended that you determine the current carrying capacity of the trace before you figure out the exact trace width. Of course, other external factors should be taken into consideration. When it comes to fab and assembly, do not forget about contaminant pollution or dust since the excess of pollution leads to partial broken traces.

Better DFM by Sierra Circuits

Minimizing Losses and Sierra Circuits Capabilities

The criticality of the trace width calculation also depends on parameters including PCB copper foil cross-sectional area, maximum current carrying capacity and consistent temperature rise.

Additionally, parameters such as conductive material selection and current carrying capacity vary as per types of conductors including internal conductors and external conductors. Also, the maximum current carrying capacity of internal conductors is half of that of external conductors. The copper foil cross-sectional area is directly proportional to the trace width. We can also say that the rising in the temperature and maximum current carrying capacity are dependent on external and internal conductors.

The standard trace width is 4 mils. The minimum spacing is done to limit excess of losses. Usually, the size of traces on an outer layer shouldn’t be below 4 mils, as plating needs to be performed on these traces.

2. Line Spacing

PCB Trace Spacing Graphic

Let’s talk about the importance of PCB line spacing for creepage and clearance. Spacing between PCB traces is another critical DFM issue manufacturers look out for during signal checks. Spacing between traces helps maintain a distance between two traces, thus avoiding flashover or tracking between electrical conductors. The flashover or tracking are defined as an electric breakdown along the surface of the PCB. Flashover can occur along the junction of the conductor trace and insulator. To avoid flashover or tracking between electrical conductors, a few standards and rules were set up in the industry. Factors, such as voltage, application and type of assembly, significantly impact spacing requirements as well. It is difficult to derive a single solution to decide specific spacing requirements to this DFM issue. Various methods and calculations are implemented in order to calculate the proper distance between two traces.

Why Is Spacing Important?

The growing importance of miniaturization in electronic circuitry is driving PCB manufacturers toward reducing size and increasing component density on circuit boards. This helps achieve miniaturization and reduces the costs. This mindset is not only confined to handheld electronic equipment but also prevalent in the entire consumer electronic sector across the globe. The current trend towards miniaturization of electronic circuitry pose substantial challenges to the designer, specifically in mixed technology that includes high-voltage circuits.

Earlier, high-voltage multi-boards like solar energy converters incorporated a separate high-voltage board in the design. With miniaturization, we can now merge multiple circuit boards using mixed technologies (analog, digital, and RF circuits). Design considerations have become a primary concern for PCB manufacturers as high-voltage circuits require additional rules to form increased electrical clearances and isolation for operator safety.

Sierra Circuits has developed certain categories in terms of spacing requirement with respect to copper weight:

Start CopperMinimum Capability in Mils (Outer Layers)Minimum Capability in Mils (Inner Layers)
Line WidthSpacing Between ConductorsLine WidthSpacing Between Conductors
5 microns2322
9 microns332.52.5
1/2 oz4432.25
1 oz6644.25
2 oz8866.25
3 oz121278
4 oz1414810

Clearance Requirements

PCB Clearance Requirements

Clearance is a crucial parameter while considering spacing between PCB traces. The clearance is defined as the minimum distance through air (medium) between two conductors. Lower clearance among traces can lead to the overhead clearance; overhead clearance may lead to over-voltage, which will result in an arc between neighboring conductive traces. This is a virtually instantaneous fault that does not recur until another such over-voltage event. Faults resulting from insufficient spacing for creepage can take much longer to occur.

The trace gets stemmed due to contamination of dust particles and moisture, thus resulting in current leakage from one or two conductors. This can cause a slow breakdown of the surface of the insulating material between them. Breakdown of the surface may be caused due to a voltage spike. The constant high voltage along with an insulating material whose comparative tracking index (CTI) is too low will definitely lead to breakdown of the surface.

The measurement of clearance depends on factors such as the PCB material, applied voltage, and temperature variations. The environmental conditions, such as temperature variations, play a major role in deciding the value for permissible clearance. Additionally, other environmental parameters, such as humidity, decide the breakdown voltage of air and affect the likelihood of arcing. The contamination of dust on the surface of the PCB can cause shortening of the distance between conductors.

Creepage Requirements

PCB Creepage Requirements

Creepage is defined as the shortest distance between two conductors on a PCB along the surface of the insulation material. Creepage is measured along the surface of the insulation material as opposed to clearance, which is measured in air (medium). Factors such as board material and environment conditions, have an effect on creepage requirements. Moisture and particulate accumulation will shorten creepage distance.

Several errors occur while deciding the creepage distance during a high-density design, owing to the complexity of the design. However, several measures are implemented to avoid these errors, such as moving tracks and increasing the surface distance in your design. Designers can avoid spacing errors by adding a slot between traces or placing vertical barriers of insulation. Designers can increase the creepage distance by various tricks instead of changing the trace layout on the board.

Solving Creepage and Clearance Issues

It is quite hard for designers to provide adequate clearance during the layout design stage. But major spacing reduction can be established by adopting a double-sided assembly and by the implementation of insulating materials.
For high-voltage nodes, insulating materials act as a sheet barrier, which also covers overexposed high-voltage leads. As most of the board components are SMDs, the circuits that require clearance can be placed on the top and bottom sides of the board. You should maintain clearance from through-hole connection points and the bounding surface.

Usually, the nodes present in the same high-voltage circuits at the same potential do not require increased clearance or creepage between them. But they require clearance to low-voltage circuits. With respect to this, try to keep high-voltage circuits on the top and low-voltage circuits at the bottom of the PCB.

Tricks, like incorporating V-groove, parallel-sided notch, or placing a slot in your design can effectively solve your creepage issues. So far, we have understood creepage is the spacing between electrical nodes over an insulating surface. We are treating it as the space between conductors on the surface or internal layers of a PCB.

So far, we have understood creepage is the spacing between electrical nodes over an insulating surface. We are treating it as the space between conductors on the surface or internal layers of a PCB.

3. Hole Registration

Why isn’t the annular ring you design the one you get?

One of the biggest DFM issues PCB houses deal with is the placement of the drilled hole, which is called hole registration. The accuracy of the hole registration is evaluated by calculating the drilled hole from the target. Various methods are adopted for measuring the hole registration accuracy. This image shows a displacement of the hole registration from its actual position. Figure A shows an ideal hole registration, while Figure B shows a displacement of the hole registration from its actual position. The actual deviation is represented by the symbol ‘L’ in Figure B. Misregistration of the hole can lead to a violation of the minimum annular ring requirement, which should be avoided at any cost.

Check for PCB Hole Registration as DFM Issues

4. Missing Copper

After designers generate an IPC netlist out of a schematic, that list should be purposefully used to avoid missing interconnections. These missing interconnections can result in missing copper that designers must check by themselves. It is expected from designers to generate an IPC netlist. PCB manufacturers can perform mismatch analysis and clarify eventual errors.

5. Featured Connection

Unconnected nets are not a good idea and often cause DFM issues. It can become a source of electromagnetic noise. Designers should remove unintended ground conductor thin traces in copper flooded areas.

6. Unconnected or Dangling Lines

When designing a complex board, you may find yourself left with unconnected lines, which are always difficult to locate. During PCB manufacturing, these unconnected lines can result in hairline short defect. However, several design constraints with respect to form factor or manufacturing budget can reduce such defects. The signal checklist allows the identification and correction of these DFM issues. Designers can themselves correct such errors by allowing a larger clearance between copper connections and pads.


Material Selector by Sierra Circuits


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