Delay is frustrating, whether in our daily lives or the devices we use for our convenience. Propagation delay/time delay inhibits the intended functions of the devices. When I say ‘devices,’ I am trying to draw your attention towards the components responsible for a product’s basic functionality. These components are arranged in a specific manner based on a circuit etched on a PCB.
PCB traces are the signal carriers in most of the devices used in today’s electronic industry. A good PCB design must ensure timely delivery of the signal from the source to the load by adjusting trace impedance and trace length so that the propagation delay could be controlled.
High-speed interfaces such as DDR3, HDMI, Ethernet, SATA, PCI Express, USB, etc. are used for fast data transfer and are prone to time delay related issues. That is why while designing a PCB with high-speed signals, synchronization between clock and data signals and between source and destination components is critical. If they are not in sync, the data will get corrupted.
In this post, we will discuss and make you understand the time delay effects concerning signals in a PCB.
- What is propagation delay in a PCB?
- Why does the propagation delay occur?
- What is the difference between transmission delay and propagation delay?
- How propagation delay affects the signal speed on a PCB trace?
- How is signal speed calculated?
- How is the propagation delay measured?
- Signal speed on an interconnect
- How can propagation delay be reduced/controlled?
- Trace length tuning/matching
- Controlling propagation delay with controlled impedance traces
- High-speed PCB design rules for propagation delay reduction
- Think about these parameters before choosing a high-speed PCB design software
- Materials for high-speed PCBs
- Propagation delays for a few PCB materials
- Correlation between signal loss and frequency traces
What is propagation delay on a PCB?
The propagation delay on a PCB trace is the one-way (source to load) time required by a signal to travel on that trace. It is expressed in time per unit length. The propagation delay is the function of the dielectric constant (Er) and the trace geometry/structure. For a given PCB laminate and a given dielectric constant, the time delay is fixed for various impedance lines. To learn more read how to choose PCB materials and laminates.
Why does propagation delay occur?
Stray capacitance is responsible for the time delay in any circuit. We do not intentionally employ capacitors in a circuit; still, there is capacitance. The overall capacitance depends upon their relative sizes and geometry of the traces. The stray capacitance includes capacitance between traces, the capacitance between traces and the adjacent ground plane, and between the traces and free space.
The effect of the stray capacitance results in signal delays. The bottom line is when a digital signal changes state, it takes some time to make the transition at the destination because of the stray capacitance that has to be charged/discharged.
High-Speed PCB Design Guide8 Chapters - 115 Pages - 150 Minute Read
- Explanations of signal integrity issues
- Understanding transmission lines and controlled impedance
- Selection process of high-speed PCB materials
- High-speed layout guidelines
What is the difference between transmission delay and propagation delay?
Transmission delay and propagation delay can be used interchangeably, but they need to be handled differently when the system is required to be analyzed in analog/digital aspects.
Logic signals’ timing across PCB trace runs can be calculated by the following transmission line approaches:
Approach 1: Terminate the transmission line by its characteristic impedance when the one-side time delay of the PCB trace equals or is more than one-half of the rise/fall time of the applied signal.
Example: A 2-inch microstrip line over an Er of 4 would exhibit a delay of about 270ps. Using the above-mentioned approach, the termination would be accurate whenever the signal rise time is less than 500ps.
Approach 2: Use 2-inch PCB track length/nanosecond (rise/fall time) approach. If the signal trace surpasses the trace length criteria, then termination must be used.
Example: The PCB tracks designed for high-speed logic with rise/fall time of 5ns should be terminated by their characteristic impedance if the track length is equal to or more than 10 inches.
PCB Transmission Line eBook5 Chapters - 20 Pages - 25 Minute Read
- What is a PCB transmission line
- Signal speed and propagation delay
- Critical length, controlled impedance and rise/fall time
- Analyzing a PCB transmission line
How propagation delay affects the signal speed on a PCB trace?
When a PCB operates at a high-frequency, its tracks’ behavior needs to be considered as transmission lines. Controlled impedance calculations are very important for these transmission lines so that signal reflections, crosstalk, noise, and ground bounce could be mitigated. These issues require special attention since they may impose a threat to signal quality, causing entire system failure. This is the reason we need to know the speed at which the signal is propagating via transmission lines and the propagation delay associated with it.
How is signal speed calculated?
Electromagnetic signals travel in vacuum/air at the same speed as the light that is:
Vc = 3 x 108 m/s = 186,000 mils/s = 11.8in/ns
For the microstrip/stripline PCB design, the signal speed is calculated as:
Where Vc is the velocity of light in vacuum/air.
Ereff is an effective dielectric constant for microstrips, and its value lies between 1 and Er.
Ereff = (0.64 Er + 0.36)
It signifies that the signal speed on a PCB is less than that in air. If the Er of the PCB material is 4, then the signal speed on a stripline design is half of that in air, about 6in/ns.
How is the propagation delay measured?
Let’s calculate the propagation delay/time delay using trace length and vice-versa. Mathematically, time delay is tpd:1/v. Where v is the speed of the signal in a PCB transmission line. In vacuum/air, it’s equal to 85ps/in.
On PCB transmission lines, tpd is given by:
Signal speed on an interconnect
When a voltage is applied between the signal and return path of a transmission line, the signal propagates down the transmission line. There is always a voltage distribution between the signal and return path. The voltage distribution on a transmission line looks like the below image.
How can propagation delay be reduced/controlled?
We cannot change the speed of the clock signal, but we can surely change the time of arrival of the signal by altering the PCB trace length. A slight change in the trace length can help the PCB components to acquire their settled state by maintaining sync with the clock signal at the same time.
Clock skew calculation for different PCB components can also help to compensate for the propagation delay/time delay problem. Meandering is another way that can give your signals the desired time to achieve the full level before the next clock pulse comes. It provides the clock pulse, just the perfect amount of delay. In best practices, it is good to meander differential traces together, and close coupling must be maintained. So, how do you decide which traces have to be meander?
- Identify the longest signal trace and meander the remaining traces in a net to sync the signal across all the traces.
- Adjust the clock trace length that connects the components in the given net.
- Delay the clock pulse by the time until the ICs can rise to the full voltage applied.
Note: In a signal net, traces with mismatched length are always matched to the trace having a maximum length. Meanders are added to the shorter traces so that their length can be increased.
Trace length tuning/matching
Due to timing mismatch, the signals traversing the different traces in a PCB reaches the load at different times. Delay tuning is essential to ensure that data arrives at the load at the accurate time for multiple parallel interconnects, traces in a differential pair, and with a clock signal. Trace length tuning is performed to tackle signal delay times.
Both delay and trace length tuning reflect the same idea. For length tuning, the lengths of the signal traces can be set in a matched group of nets. As we know, timing delay is inevitable. We can only adopt measures to control it. By placing the traces having the same length in a matched group, we try to ensure that all signals traversing these traces arrive within a fixed timing delay. Now the question is what to do if there are two mismatched signal traces in a matched group? Signals traversing such traces can be synchronized by adding delay to the shorter signal trace known as meandering.
Theoretically, the receiver instantly receives any waveform/signal sent by the transmitter. We also assume that clock signals have zero time gaps and are processed concurrently at the receiver. But the reality is different. If there is a slight mismatch in the length of the PCB traces then there are chances that signals may not arrive at the receiving pins simultaneously. PCB trace tuning ensures that the traces in which the time of arrival of critical signals is matched to equal length.
Controlling propagation delay with controlled impedance traces
Different trace geometries/structures can be used for controlled impedance traces. The trace configurations we are discussing here are based on IPC standard 2141A.
- Wire microstrip: It is made up of a discrete insulated wire separated by a fixed distance over a ground plane. The dielectric can be either the insulation wall of the wire or a combination of this insulation and air.
- Surface microstrip: In a two-sided PCB design with a ground plane on one side, a signal trace on the other side can be designed for controlled impedance. This trace structure is known as surface microstrip or simply microstrip.
- Embedded/symmetric stripline: In a multi-layer PCB, this arrangement implements the signal trace between a power and a ground plane. The return current path for a high-frequency signal trace is located above and below the signal trace on the planes. So, the high-frequency signal remains inside the PCB, resulting in fewer emissions and shielding from other spurious signals.
Note: Ground plane is at zero potential with a low-impedance reference plane having a larger area.
- Coplanar structure: A coplanar waveguide structure has the signal trace and the return path conductor on the same layer of the PCB. The signal trace is at the center and is surrounded by the two adjacent outer ground planes; it is called ‘coplanar’ because these three flat structures are on the same plane. The PCB dielectric is located underneath. Both microstrips and striplines may have a coplanar structure.
High-speed PCB design rules for propagation delay reduction
Precise time delay management requires trace length calculations to implement the high-speed PCB routing accordingly. The distance between components on a PCB is very short. We don’t even think about the time taken by the signals to travel on the PCB. But in high-speed PCBs, switching takes place with edge rates less than 1ns. Such short distance between the components is of primary importance obviously if you want your system to perform without interruption.
- A designer must know the specific timing tolerances for intended PCB signals.
- Different interfaces that run at different data rates using different signalling standards. Specify different permissible length or timing mismatches. When planning for I/O channels in a PCB, a designer should look for an acceptable length mismatch and convert it into a permissible timing mismatch.
- Avoid using a substrate with a larger dielectric constant value: Generally, a substrate having larger dielectric constant results in a lower signal velocity, which is more than the allowed specified propagation delays, especially between the data line and clock.
- Focus on pin-package delays: When a signal arrives on a pin/pad of a particular component, it still needs to traverse the exposed conductor path along with the interior of the component package. While traversing the signal trace and the bond-wire associated with the internal circuitry, the signal experiences parasitic inductance and capacitance which affect its travel speed in the bond-wire compared to the trace. The bond wires also have different geometries that add to the signal delay on different pin/pad. It is advised to ask the manufacturer for the pin-package delay associated with a particular component. It is mentioned in picoseconds (ps) or as a length in mm/microns. This length should be considered while performing any delay/length tuning with signals in differential pairs or single-ended signals.
- Watch your ‘clock skew’: When clock and signal traces have different lengths, it results in a timing mismatch called clock skew. Ignoring this problem may lead to wrong data being latched. The clock delay should be greater than the greatest delay in the data signals.
- Check for skew duration: Always refer to the datasheet for the receiver component and check for the timing tolerances for data setup, latch and hold for a cycle.
- Material dispersion is a high-frequency phenomenon. Always consider it at switching frequency.
Think about these parameters before choosing a high-speed PCB design software
If you are using software that considers only the length mismatch, then you can easily calculate the correct length mismatch value for a given substrate. This length mismatch is equal to the timing mismatch multiplied by signal velocity (in/ns) in the given substrate. A good PCB design software should offer the following things to target propagation delay:
- Interactive routing capabilities
- Smart length tuning
- IPP enhancements (instant access to new and existing functions)
- Dynamic data model (to speed-up netlist creation)
Materials for high-speed PCBs
We all know that signal speed is affected not only by trace geometry, trace location but also by substrate material. The dielectric constant of the trace governs the signal speed on it. Let us see an example; if we suspend a trace in vacuum, only the trace’s dielectric constant will affect the speed. If the trace is on the PCB surface, then the signal speed will also be affected by the other dielectrics present nearby; this is what happens in a PCB. Traces run over the PCB substrate material (having a fixed dielectric constant value). The substrate’s dielectric constant and the dielectric of air and solder mask play a major role in deciding the signal speed. This is called an effective dielectric constant (Ereff). Board thickness also affects the speed of the signal. For more information, check out Learning about High-Speed PCB Design.
FR4 can be used for high-speed PCB design when the layers are laminated with high-speed laminates such as Rogers. At high-frequency, FR4 experiences dispersion, which increases the speed and decreases the propagation delay. Electromagnetic absorption in FR4 generates more signal attenuation for the traces associated with it. Thus, high-speed laminates are used below high-speed traces along with FR4 laminates, especially at frequencies above 5GHz.
Propagation delays for a few PCB materials
The signal speeds and propagation/time delays for a few PCB materials are given in the table below:
Correlation between signal loss and frequency
The graph shown below depicts that there’s a direct correlation between signal loss and frequency. At the same time, we can also see that certain materials are less lossy than others. This graph shows which materials could possibly perform electrically better at higher speeds.
The primary function of a PCB is to transfer the signals accurately and without loss between the devices. Propagation delay or time delay plays an important role in the proper functioning of a high-speed board. It can not be avoided completely but can be reduced by adopting different trace configurations followed by accurate length matching and meandering if required. You should know about the controlled impedance traces in your design, material dielectric, and which traces would need delay measurements. You also need to know the relationship between signals such as clock and data for the proper functioning of the board.