If you are planning to design a PCB, you should consider several technical specifications related to manufacturing like material selection and stack-up. One such important factor is copper distribution. In this article, we will talk about balanced copper distribution, copper weight, and techniques, such as thieving, that help to achieve even copper distribution on circuit boards.
What is balanced copper distribution in PCBs?
When some parts of a PCB have more copper than the other regions, it will lead to unbalanced copper distribution. This might lead to board failure or improper functioning. A well-balanced copper distribution can avoid this from happening. Besides electrical and thermal features, it plays important roles in many aspects:
Role of copper
- Copper plating on a PCB – It reduces the ground line impedance and voltage drop. This reduces the noise. Along with this, the efficiency of a power supply can be improved.
- Traces – The copper layer is etched to form traces. Traces carry signals all over the board. They establish strong interlayer connections.
- Heatsinks – Copper layers act as heatsinks in a very high-power circuit. Thus, additional heatsinks can be eliminated to reduce manufacturing costs.
From the above aspects, we can conclude that any unbalanced copper can cause huge problems in a design. One common problem that arises due to this is board warping. We will talk about warping in the later sections.
Things to avoid for balanced copper distribution
There might be several factors behind asymmetric copper thickness on a board. Some major issues are analyzed below:
Improper balancing of stack-up
Balancing a stack-up means having symmetrical layers in your design. The motive is to discard the risk zones where deformation can occur during the stack-up assembly and lamination stage. The best way to do this is to start the stack-up design from the center of the board and position the thick layer there. Usually, a PCB designer’s strategy is to mirror the top half of the stack-up with the bottom half.
Uneven dielectric layer thickness
Board layer stack-up management is a crucial element in designing high-speed boards. To keep symmetry in the layout, the safest practice is to balance the dielectric layer. The dielectric layer thickness should be aligned symmetrically just like the layer stack-up.
But sometimes it is hard to achieve uniformity in dielectric thickness. This is due to some manufacturing constraints. In this case, the designer will have to relax the tolerances and allow uneven thickness and some amount of warpage.
Uneven circuit board cross-section
One of the familiar unbalanced design issues is improper board cross-section. Copper deposition gets larger in some layers than the rest. This problem arises from the fact that the consistency of copper is not maintained over different layers. At the time of assembly, some layers get thickened and others with low copper deposition remain thinner. When pressure is exerted on the board laterally, it gets deformed. To avert this, copper coverage must be symmetrical with respect to the center layer.
Hybrid (mixed materials) stack-up
Sometimes the design incorporates the use of mixed PCB materials in the stack-up. Different materials have different thermal coefficients (CTC). This type of hybrid construction increases the risk of warpage during reflow assembly.
Effects of unbalanced copper distribution
Variation in copper deposition causes warpages in PCBs. Some of the defects are mentioned below:
Warpage is nothing but the deformation of the board’s shape. During baking and handling of the board plate, mechanical expansion and compression occur differently in copper foil and substrate. It causes deviation in their expansion coefficients. Subsequently, the generated internal stress on the board leads to warpage.
Based on the application, the PCB material can be either fiberglass or any other composite material. During the manufacturing process, the board undergoes several heat treatments. If the heat is not uniformly distributed, and the temperature exceeds the CTE and the board gets warped.
If copper coverage is not balanced, cylindrical or spherical curvature is formed on the PCB layer. In simple language, you can say the four corners of a table are fixed and the top of the table rises above. It is known as a bow, which is a result of technical faults. The bow results in tension on the surface in the same direction as the curve. Further, it leads to random current flow across the board.
Twist is influenced by board material and its thickness. It happens when any one corner of a board is not aligned with others symmetrically. A particular surface diagonally rises up, then the other corners get twisted. The fact is quite similar to when you pull up a mat from one corner of a table and the other corner gets twisted. Refer to the figure below.
Resin void is nothing but a consequence of improper copper plating. During the assembly, pressure is applied in an asymmetric manner on the board. As pressure is a lateral force, the surface having thin copper deposition oozes out resins. This creates voids in that location.
Fails to meet the class 3 standard
Class 3 standard is the highest and toughest to achieve among the three fundamental categories of PCB. The products under class 3 rarely compromise the manufacturing specifications. Due to unbalanced copper deposition beyond the tolerance limit, the main circuitry gets distorted. This eludes the product’s failure to realize the class 3 requirements.
IPC Class 3 Design Guide8 Chapters - 23 Pages - 35 Minute Read
- IPC guidelines for manufacturing defects
- IPC standards for assembly processes
- Common differences between the classes
- IPC documents to set the level of acceptance criteria
Measurements of bow and twist
As per IPC-6012 the maximum allowance for bow and twist is 0.75% on a board with SMT components and for others, it is 1.5%. Based on this standard, we can also calculate the bow and twist for a particular PCB size.
Bow allowance= Board length or width ✖ percentage of bow allowance ∕ 100
Twist measurement involves the diagonal length of the board. Considering the fact that the board is constrained from one of the corners and the twist is acting in two directions, factor 2 is included.
Maximum allowable twist = 2 ✖ Board diagonal length ✖ percentage of twist allowance ∕ 100
Here, you can see the example of a board having length and width respectively 4’’ and 3’’, and a diagonal length is 5’’.
Bow allowance across the length= 4 ✖ 0.75 ∕ 100 = 0.03 inches
Bow allowance across the width= 3 ✖ 0.75 ∕ 100 = 0.0225 inches
Maximum allowable twist = 2 ✖ 5 ✖ 0.75 ∕ 100 = 0.075 inches
Techniques to balance copper distribution
Cross-hatching is a process in which certain copper layers take the shapes of latticework. It actually involves regular openings at regular intervals and almost looks like a large sieve. The process creates small openings in the copper plane. The resin will bond strongly to the laminate through copper. This creates a stronger bond and better copper distribution, mitigating the risk of deformation. Following are some benefits of hatched-copper plane over solid pour:
- Controlled impedance routing in high-speed boards.
- Allows wider dimensions without compromising the flexibility of circuit assembly.
- Increases the copper amount under the transmission line, and increases the impedance.
- Provides mechanical support for dynamic or static flex boards.
Use of thick copper board
Prefer thicker copper boards than thinner ones if your design permits. The chance factor of bow and twist becomes high when you use a thin board. This is because there isn’t sufficient material to maintain the stiffness of the board. Some of the standard thicknesses are 1mm, 1.6mm, and 1.8 mm. Below 1mm, the risk of warping doubles than thicker boards.
The conductor traces should be placed uniformly across a board. Avoid copper nests as far as possible. Traces should be distributed symmetrically on each layer.
Copper thieving is a process of depositing non-conductive copper features to counterbalance the current flow in a PCB during the plating process. Current accumulation will be high in the areas where isolated traces are present. This causes under-etching of traces resulting in a mushroom profile instead of smooth squared edges.
This can be avoided by thieving which steals the stockpiled current and balances the current flow while plating the area where the metal is sparse. Moreover, cutting down the metal in the trace impacts the characteristic impedance and causes SI problems in the circuit.
Copper thieving involves adding small circles, squares, or even a solid plane of copper to the large vacant spaces on the board. It will distribute the copper profile evenly throughout the board. Special measures should be taken so that thieving does not make connections with any net, and disturb the functionality of the defined CI or RF traces.
Benefits of implementing copper thieving
- Controlled finished thickness: Copper thieving enables you to balance the copper and dielectric percentages throughout the board surface. Due to this, you can achieve consistent finished thickness.
- Even plating and etching: Another reward of copper thieving is accomplishing controlled etching/plating and uniform current distribution in a sparse zone.
- Avoids outgassing, delamination, bow, and twist: Since the copper distribution is uniform, the chances of outgassing, delamination, bow, and twist are significantly less.
- Decreased need for excess etch: Etching involves removing the excess copper to reveal the copper pattern with the help of a chemical solution. But if the etching solution gets saturated with copper, it becomes ineffective. Hence, the etching procedure has to be cycled again. Copper thieving decreases excessive etching and reduces the overall cost.
How can you implement copper thieving?
There are several design tools available that assist you to add copper thieving automatically. You can specify the shape, size, and spacing of the pattern in your EDA tool. The shape doesn’t matter if copper is poured evenly throughout the board.
Copper thieving sometimes works as EMI shielding when incorporated in the form of a solid plane. It is essential to place this plane in the proper position and with correct spacing regulations. Otherwise, it may adversely impact the signal integrity of your design.
Why thieving is bounded in the outer layer
When implementing copper thieving, you need to ensure that traces are not present below the pattern. This can adversely affect the impedance of those traces. To avoid this, mention the requirement and the accurate location of thieving in the fab drawing.
Outer layers of the circuit board involve uneven distribution with CI traces, component securing pads, and holes for press-fit connectors. If copper thieving is not applied here, the isolated features will be plated with a greater amount of copper than the dense area of the board. This results in fragile connections. To avoid this, ensure sufficient copper is poured to plate vias and component mounting holes.
If a large copper area is required, the open areas are filled with copper. It is done to maintain a counterbalance with the symmetrically opposite layer.
Symmetry in power plane
It is very important to maintain copper thickness in each signal or power plane. Power planes should be symmetric. The renowned senior applications engineer of Keysight, Heidi Barnes told us during DesignCon, “One of the challenges is the power layers. The simplest form is to put the power and ground layers in the middle. If you can get the power and the ground closer together, the loop inductance is very much smaller so the spreading inductance is less.”
Prepreg and core symmetry
Just keeping the power plane symmetrical is not sufficient to arrive at even copper cladding. It is also important to match the prepreg and core in the layering and thickness issues.
Importance of copper weight in PCBs
Fundamentally, copper weight is a measure of copper thickness on the board. A copper of a specific weight is rolled on one square foot area of a layer in the board. The standard copper weight we use is 1 oz or 1.37 mils. For example, if you are using 1 oz of copper for a 1 sq ft area, the thickness of copper is 1 oz.
The table below provides the copper thickness values in oz, mils, inch, mm, and µm.
Copper weight is the determinant factor of the current carrying capacity of the board. If your design has high voltage, current, resistance, or impedance requirements, you can modify the copper thickness.
There is no generalized definition of heavy copper. We do use 1 oz as standard copper weight. But, if your design demands more than 3 oz, it is defined as heavy copper.
Primarily, you can conclude that the higher the copper weight, the higher will be the current carrying capacity of a trace. The thermal and mechanical stability of a board also rises. It is now more tolerant to high-current exposure, excessive temperature, and frequent thermal cycling. All of these can cripple a regular board design. Other advantages are:
- High power density
- Greater capacity to hold several copper weights on the same layer
- Increases heat dissipation
Heavy copper boards find applications in the following fields:
- Computer and automotive industries
- Military and industry control
- Power supply and distribution
- Power conversion
- Solar panel and welding equipment manufacturing
- Electrical vehicles with lithium batteries
At times, you need to lower the copper weight to achieve a specific impedance. It is not always possible to adjust trace length and width, hence implementing lower copper thickness is one of the feasible ways. You can use our trace width calculator to design the right traces for your boards.
Spacing with copper weight
The spacing between traces needs to be regulated when you use thick copper cladding. Different designers have different specifications for this. Here is an example of the minimum space requirement with respect to copper weight.
|Space between copper features and minimum trace width
|3.5 mil (0.089mm)
|8 mil (0.203mm)
|10 mil (0.254mm)
|14 mil (0.355mm)
As the copper weight increases, the overall cost elevates. Naturally, the manufacturing time will also be more. The reason for the additional cost is not only for excess thickness, it also includes additional shipping weight, quality assurance, process efficacy, and increased labor time.
Sierra Circuits efficiently analyzes the suitability of heavy copper for a particular design. As per the DFM guidelines, our DFM engineer decides the etching time for heavy copper boards. As discussed earlier, unbalanced copper distribution can cause warpage in the PCB. Practically, 0.7% of the warpage (of the board diagonal length) is permissible. Beyond this tolerable limit, the complete design can be a failure. Here, the manufacturing team always inspects copper distribution and symmetrical build-ups to avert manufacturing problems. If you have any questions regarding copper weight and balanced copper distribution, please feel free to post your comment below.
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