Every day, PCB designs and components become smaller, faster – in other words, more complicated. It is now crucial to understand your critical nets and traces, impedances, and how the board impacts the performance of the signal.
The time of simple interconnecting traces and conductors is over. Nowadays, the speeds of the circuits are increasing day by day, and signals in the GHz range are common. Hence, the controlled impedance of traces plays an important role in signal integrity and the performance of circuit boards.
In this article, we will be covering the following topics:
What is a controlled impedance?
Controlled impedance is the characteristic impedance of a transmission line formed by PCB traces and its associated reference planes. It is relevant when high-frequency signals are propagating on the PCB transmission lines. Controlled impedance is important for solving signal integrity problems, which is the propagation of signals without distortion.
The impedance of circuits is determined by the physical dimensions and the dielectric materials of the PCB. It is measured in Ohms (Ω). Types of PCB transmission lines that require controlled impedance are single-ended microstrip, single-ended stripline, microstrip differential pair, stripline differential pair, embedded microstrip, and co-planar (single-ended and differential).
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Why do you need controlled impedance?
Typically, you will need controlled impedance for PCBs used in high-speed digital applications, such as RF communication, telecommunications, computing using signal frequencies above 100MHz high-speed signal processing, and high-quality analog video such as DDR, HDMI, Gigabit Ethernet, etc.
At high-frequency, the signal traces on a PCB act like transmission lines, which have impedance at each point on the signal trace trajectory. If this impedance varies from one point to the next one, there will be a signal reflection whose magnitude will depend on the difference between the two impedances. The larger the difference is, the greater the reflection will be. This reflection will travel in the opposite direction of the signal, which means that the reflected signal will superimpose on the primary signal.
As a result, the original signal will be distorted: the signal intended to be sent from the transmitter side would have changed once it gets to the receiver side. The distortion may be so much that the signal may not be able to perform the desired function. Therefore, to have undistorted signal travel, the PCB signal traces must have a uniform controlled impedance to minimize signal distortions caused by reflections. This is the first step to improve the integrity of the signals on the PCB traces. For better understanding, read the effects of high-speed signals in a PCB design.
A uniform transmission line on a PCB has a definite trace width and height and is at a uniform distance from the return path conductor, usually a plane at a certain distance from the signal trace.
Factors that affect the controlled impedance
Factors that influence the PCB impedance tolerances include materials’ resin content percentage, Dk values of the resin and the type of the glass cloth used, and other physical PCB tolerances like trace height and width at the top and bottom of the trace. When you give Sierra your PCB design– copper patterns, hole patterns, and final material thicknesses– we laminate the copper layers into a single circuit board. We manufacture your PCB with the right pattern sizes and positions within certain tolerances. You must ensure that your manufacturer provides you the right size, position, and tolerance of your etched features. If not, your boards will vary from each other, making debugging performance-related issues very difficult.
Why is it good to specify the dielectric of the board instead of CI?
The impedance of traces is also defined by the PCB materials used on the board. The dielectric constant of the materials and the expected impedance based on certain parameters is called a controlled dielectric. If you like math, you can take the controlled dielectric approach to control the impedance you need. Once you make your calculations, you can specify the dielectric space required between the copper layers in your fab. Then, layout your traces with the right trace and space.
In this scenario, it still might be better to request a controlled impedance board instead of a controlled dielectric board. For controlled dielectric, are you specifying the types of glass cloths to be used? The resin percentage of the materials? If not, then you can’t be sure what your manufacturer is using. Also, are you ensuring that the trace widths are within tolerance? The burden falls on you if you request for a controlled dielectric board.
It is not hard for us to calculate the impedance for you. Just let us know which traces have to be controlled and what the required impedance is. Sierra does two types of impedance controls: controlled dielectric and impedance control.
How to design a board with controlled impedance?
You should follow the below-mentioned controlled impedance routing tactics for designing a PCB:
Determine which signals require CI
Most of the time, electrical engineers specify which signal nets require a specific controlled impedance. However, if they do not, the designer should review the datasheets of the integrated circuits to determine which signals require controlled impedance. The datasheets usually provide detailed guidelines for each group of signals and their impedance values. The spacing rules and information on which layer to route specific signals may also appear in the datasheets or in the application notes. DDR traces, HDMI traces, Gigabit Ethernet traces, RF signals are some examples of controlled impedance traces.
Annotate the schematic with impedance requirements
The design of a board starts with the design of the circuit schematics by the design engineer. The engineer must specify controlled impedance signals in the schematic and classify specific nets to be either differential pairs (100Ω, 90Ω or 85Ω) or single-ended nets (40Ω, 50Ω, 55Ω, 60 Ω or 75Ω). It’s a good design practice to add N or P polarity indication after the net names of the differential pair signals in a schematic. The engineer should also specify particular controlled impedance layout design guidelines (if any) to be followed by the layout designer, either in the schematic or in a separate “Read Me” file.
Determine the trace parameters for controlled CI
A PCB trace is defined by its thickness, height, width, and dielectric constant (Er) of the PCB material on which the traces are etched. While designing controlled impedance PCBs, it is essential to take care of these parameters. You can provide the manufacturer with the number of layers, the value of the impedance traces on specific layers (50Ω, 100Ω on layer 3), and materials for PCB designing.
The manufacturer gives you the stackup that mentions the trace widths on each layer, the number of layers, the thickness of each dielectric in the stackup, trace thickness, and PCB material. He also takes care of the controlled impedance requirements by calculating the feasible thickness, width, and height for the traces that need impedance control. Stick to the following relationships to know how impedance depends on dimensions:
- Impedance is inversely proportional to trace width and trace thickness.
- Impedance is proportional to the laminate height and it is inversely proportional to the square root of laminate’s dielectric constant (Er).
Avoid these routing mistakes when designing for controlled impedance
Differentiate CI traces from other traces
The controlled impedance trace widths must be distinguishable from the remaining traces on the board. It allows the PCB manufacturer to quickly identify them and make suitable changes to the trace width if necessary, to achieve a specific impedance. For example, if you require a 5mil trace to achieve 50Ω impedance and if you have also routed other signals with 5mils width, it will be impossible for the PCB manufacturer to determine which ones are the controlled impedance traces. Therefore, you should make the 50Ω impedance traces 5.1mils or 4.9mils wide.
The table below shows trace widths and spacings for controlled impedance on different layers. Non-impedance signal traces should not be routed with 3.5, 3.6, 4.2, 4.25, and 4.3mil trace widths.
Maintain symmetry in differential pair routing
High-speed differential pair signal traces need to be routed parallel to each other with a constant spacing between them. The specific trace width and the spacing are required to calculate the particular differential impedance. The differential pairs need to be routed symmetrically. You should minimize areas where the specified spacing is enlarged due to pads or the ends.
Adequate spacing b/w controlled impedance traces, other traces, and components (3W and 2W rule)
To reduce crosstalk, the spacing b/w traces should be 3W or at minimum 2W. Note that this rule does not apply to the spacing b/w differential pairs.
Placement of components, vias, and coupling capacitors
Components or vias should not be placed between differential pairs, even if the signals are routed symmetrically around them. Components and vias create a discontinuity in impedance and could lead to signal integrity problems. For high-speed signals, the spacing between one differential pair and an adjacent differential pair should not be less than five times the width of the trace (5W). You should also maintain a keep-out of 30mils to any other signals. For clocks or periodic signals, you should increase the keep-out to 50mils to ensure proper isolation.
If high-speed differential pairs require serial coupling capacitors, they need to be placed symmetrically, as shown in the below figure. The caps create impedance discontinuities, so placing them symmetrically will reduce the amount of discontinuity in the signal. For more insight, read how to limit impedance discontinuity and signal reflection in PCB transmission line.
You should minimize the use of vias for differential pairs, and if you do place them, they need to be symmetrical to minimize discontinuity.
Length matching will achieve propagation delay matching if the speed of the signals on various traces is the same. Length matching may be required when a group of high-speed signals travel together and are expected to reach their destination simultaneously (within a specified mismatch tolerance).
The lengths of the traces forming a differential pair need to be matched very closely; otherwise, that would lead to an unacceptable delay skew (mismatch between the positive and negative signals). The mismatch in length needs to be compensated by using serpentines in the shorter trace. The geometry of serpentine traces needs to be carefully chosen to reduce impedance discontinuity. The figure below shows the requirements for ideal serpentine traces. Read our post on how we manufacture controlled impedance PCBs.
The serpentine traces should be placed as near as possible to the source of mismatch. It ensures the mismatch correction as soon as possible. In the figure below, you can see that the mismatch occurs on the left set of vias, so the serpentine needs to be added on the left rather than on the right.
Similarly, bends cause mismatching making the trace on the inner bend smaller than the outer trace. Therefore, we need to add serpentines as close to the bend area. If a pair has two bends closer than 15mm, they compensate each other. Hence you do not need to add serpentines.
When a differential pair signal changes from one layer to another using vias and has a bend, each segment of the pair needs to be matched individually. Serpentines should be placed on the shorter traces near the bend. You need to manually inspect for this violation as it will not be caught in Design Rule Checks since the lengths of the total signals will be closely matched. Since the signal speed of traces on various layers may be different, it is recommended to route differential pair signals on the same layer if they require length matching. Also, check our post on how to route differential pairs in KiCad.
Reference layers for the return path of controlled impedance signals
All high-speed signals require a continuous reference plane for the return path of the signal. An incorrect signal return path is one of the most common sources for noise coupling and EMI issues. The return current for high-speed signals closely follows the signal path, whereas the return current for low-speed signals takes the shortest path available. Generally, the return path for high-speed signals is provided in the reference planes nearest to the signal layer.
High-speed signals should not be routed over a split plane because the return path will not be able to follow the trace. You should route the trace around the split plane for better signal integrity. Also, make sure that the ground plane is a minimum of three times the trace width (3W rule) on each side.
If a signal needs to be routed over two different reference planes, a stitching capacitor between the two reference planes is required. The capacitor needs to be connected to the two reference planes and should be placed close to the signal path to keep the distance between the signal and the return path small. The capacitor allows the return current to travel from one reference plane to the other and minimizes impedance discontinuity. A good value for the stitching capacitor is between 10nF and 100nF.
You should avoid both split plane obstructions and slots in the reference plane just underneath the signal trace. If the slots are unavoidable, stitching vias should be used to minimize the issues created by the separated return path. Both pins of the capacitor should be connected to the ground layer and should be placed near the signal.
When vias are placed together, they create voids in reference planes. To minimize these large voids, you should stagger the vias to allow sufficient feed of the plane between vias. Staggering the vias allows the signal to have a continuous return path.
It is preferred to use ground planes for reference. However, if a power plane is used as a reference plane, you need to add a stitching capacitor to allow the signal to change the reference from the ground to the power plane and then back to the ground. You should place a capacitor close to the signal entry and exit points and connect one end to the ground and the other to the power net.
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Add stitching vias close to the layer change vias.
If a high-speed differential pair or single-ended signal switches layers, you should add stitching vias close to the layer change vias. This practice also allows the return current to change ground planes.
If a high-speed signal trace switches to a layer with a different net as reference, stitching capacitors are required to allow the return current to flow from the ground plane through the stitching capacitor to the power plane. The placement of the capacitors should be symmetrical for differential pairs.
Controlled impedance design checklist
- The controlled impedance lines should be marked in the PCB schematic drawing.
- The differential pair trace lengths should be matched with a tolerance of 20% of the signal rise/fall time.
- High-data frequency connectors should be used.
- For microstrip construction, use unbroken ground beneath the microstrip trace.
- For stripline construction, use ground or unbroken power, over, beneath, and sides of the differential pairs. The ground and power planes provide the return currents path. It also reduces EMI issues.
Sierra’s capabilities in controlled impedance
Equipment used by Sierra Circuits for impedance measurement:
- Polar CITS – coupons only
- Tektronix 8300 – boards as well as coupons
If an impedance coupon is not functional or fails the impedance test, Sierra performs impedance testing on boards to verify if the product is within the specifications or a remake would be required with necessary adjustments.
However, it is critical to test the impedance from the boards due to the length of the traces, which depends upon the size of the board. The location of the inner layer impedance traces on the finished product is very crucial as well.
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How to use Sierra’s impedance calculator?
The first thing to do is to choose what kind of impedance you want: single-ended or differential. Check out our impedance calculator.
How to calculate single-ended impedance?
Choose the dielectric constant based on the materials listed in the box below. And choose the dielectric height based on your stack-up. Enter the SE impedance you want, the trace width, and the trace thickness (if not already pre-filled). Now click the “Calculate Impedance” or “Calculate Trace” buttons. If you want a specific trace width, you can adjust the dielectric height and the trace thickness until you achieve your desired trace width. Make sure that the impedance does not vary too much when you change the above values.
How to calculate differential impedance?
Enter the differential impedance you want, the trace width, the dielectric height, the dielectric constant, and the trace thickness. Now click the “Calculate Trace” button to get the accurate trace width. If you want a specific trace width and separation, you can play around with different values in the calculator until you achieve it. Make sure that the impedance does not vary too much. It can be +/- 2%.
Note that in both cases, Sierra’s stackup team does not check the odd mode impedance, the even mode impedance, the propagation delay, the inductance, or the capacitance. The reason is that most boards only require one or two types of impedance: single-ended and differential.
Key points to remember
Along with the usual PCB specifications, the PCB designer should also specify:
- Which layers contain controlled impedance traces?
- The impedances of the traces since there can be more than one value of impedance trace per layer.
- Separate aperture codes for controlled impedance traces, e.g., 4mil non-controlled impedance trace and 4mil-controlled impedance trace.
Remember, trace Impedance is a critical factor in the effort to control reflections. Impedance must match the driver and load.