Every day, PCB designs and components become smaller, faster – in other words, more complicated. It is now crucial to slow certain circuits down in order to allow specific functions of components to perform before others. The time of simple interconnecting traces and conductors is over.
What is controlled impedance?
Controlled impedance is the characteristic impedance of a transmission line formed by PCB conductors. It is relevant when high-frequency signals propagate on the PCB transmission lines. Controlled impedance is important for signal integrity: it is the propagation of signals without distortion.
The impedance of circuits is determined by the physical dimensions and materials of the circuit and is measured in Ohms (Ω).
How to control impedance
Factors that influence impedance PCB tolerances include materials’ resin content and tolerance, and the trace height and width at the top and bottom of the board. When you give Sierra your set of patterns – copper patterns, hole patterns and ink patterns – we combine them into a single circuit board. We manufacture your PCB with the right pattern sizes and positions within certain tolerances. It is essential that you make sure that your manufacturer can provide you the right size, position, and tolerance so your board won’t be useless.
Keep in mind that the impedance of traces is defined by more than the size of the trace. When you define a trace as an impedance control trace, the impedance matters more than the size of the feature for the manufacturer. So we might change certain specifications that you gave us in your Gerber file, such as the trace width, the trace height, and the dielectric thickness. But we will make sure that the final impedance is within the tolerance.
The impedance of traces is also defined by the PCB materials used on the board. The impedance of materials and the expected impedance based on certain parameters is called controlled dielectric. If you like math, you can take the controlled dielectric approach to control the impedance you need. Once you make your calculations, you can specify the dielectric space required between the copper layers in your fab, and then lay out your traces with the right trace and space.
If you want us to calculate the impedance for you, just let us know which traces have to be controlled, and what the required impedance is.
Sierra does 2 types of impedance controls:
- Controlled dielectric
The PCB designer gives the controlled dielectric stack-up, and we make sure to follow controlled dielectric thicknesses provided. However, impedance traces are not specified thus, the manufacturing focus is completely upon building a board within +/- 10% tolerance of the specified dielectric thickness from layer to layer.
- Impedance control
We control the impedance through the dielectric thickness, and the trace width and space. We perform a test to make sure that we achieved the desired impedance using TDR coupons. The first articles are processed in order to evaluate any discrepancies before an entire order is committed. Adjustments are made depending upon results from the first articles in order to meet the customer’s needs and manufacture the boards within the specified tolerance.
For more information, you can read our article about TDR impedance measurements.
A typical tolerance on the final impedance is +/- 10%. But Sierra is able to do +/- 5% impedance tolerance.
Common mistakes to avoid when designing for controlled impedance
- Traces crossing split planes
High-speed signals should be routed over a sold ground reference plane. The traces should not be routed across a split plane or a void in the reference plane unless it is absolutely necessary to avoid increasing impedance.
Routing high-speed signals across split planes can cause the following issues:
- Delay in signal propagation due to increased series inductance
- Interference with other signals
- Degradation of the electrical signal (it compromises the signal integrity)
Stitching capacitors can be used across split planes if the signals have to be routed over the split planes.
The capacitors provide a return path for the high-frequency current and minimize the current loop area along with any impedance discontinuity created by crossing the split plane. In the image below, you can see that the signal is routed around the void in the plane rather than across the split/void in the plane.
- Traces with no reference ground plane
Route the high-speed signals either on the top or the bottom layer and provide a complete ground reference plane on the adjacent layers – the impedance will be very high if there are no adjacent layers. The inner layers can be used for power planes and other signal routing purposes.
It is important to match the etch lengths of differential pairs and add serpentine routing as close to the mismatched ends as possible. On the image below, you can see that the serpentine is added near the pads on the left side as they are farther apart from each other and hence mismatched.
- Mismatches in length
Mismatches in length between differential pairs are a group of single-ended impedance traces which will lead to signal distortion and increase the bit error rate. The differential pairs need to be length-matched within +/- 5 mils of each other if possible.
Common mistakes to avoid in the stack-up
It is recommended to not use more than three different types of prepregs in a stack-up. Furthermore, the dielectric thickness of each prepreg layer should be less than 10 mils, otherwise it increases the chance of a greater variation in the final thickness. You should avoid using prepregs that have very low resin and high glass content: very low resin content may lead to resin starvation during lamination.
Examples of very low resin and high glass content prepregs are those that use 7628 and 2116 content glass styles. 2113 glass style is a borderline case. If possible, avoid it in a prepreg layer, unless there are no adjoining copper layers.
- Impedance trace / space
It is a good design practice that the spacing between the two traces of a differential pair should not be more than twice the width of the traces. For instance, a 4-mil differential trace should not have more than an 8-mil space. As often as possible, the trace width should not exceed twice the dielectric thickness between the target signal layer and the nearest reference layer.
Sierra’s capabilities in controlled impedance
Equipment used by Sierra Circuits for impedance measurement:
- Polar CITS – coupons only
- Tektronix 8300 – boards as well as coupons
If an impedance coupon is not functional or fails the impedance test, Sierra performs impedance testing on boards to verify if the product is within the specifications or a remake would be required with necessary adjustments.
However, it is critical to test the impedance from the boards due to the length of the traces, which depends upon the size of the board. The location of the inner layer impedance traces on the finished product is very crucial as well.
Upon failure, a cross-section is taken from the impedance coupon in order to further evaluate which factors are affecting the calculated impedance in relation to the recorded impedance. The cross-section technician measures the dielectric thicknesses depending upon the trace location, either the inner layer or the outer layer. Additionally, the trace width is measured from the bottom as well as the top of the affected impedance trace along with the copper thickness or the trace height. When it is a differential pair, the spacing between the two traces is also measured to understand whether or not the projected impedance is in alignment with the recorded impedance.
The image below displays cross-section evaluation details on a single-ended impedance trace:
A – Trace Width from Top
B – Copper Thickness or Trace Height
C – Trace Width from Bottom
D – Dielectric Thickness between Layer 2 and Layer 3 (Trace)
E – Dielectric Thickness between Layer 3 (Trace) and Layer 4
In order to determine the acceptability of the boards, Sierra uses test coupons to make sure there are no variations in the trace width, the trace thickness, and so on. We manufacture the test coupons on the same panel and under the very same specifications than the actual boards – which are too difficult to test because of the controlled impedance traces that are hard to access and not often have any trace work or pads.
How to use Sierra’s Impedance Calculator
The first thing to do is to choose what kind of impedance you want: single-ended or differential.
How to calculate single-ended impedance:
Choose the dielectric constant based on the materials listed in the box below, choose the dielectric height based on your stack up. Enter the SE impedance you want, the trace width, and the trace thickness (if not already pre-filled), and click the “Calculate Impedance” or “Calculate Trace” buttons. If you want a specific trace width, you can adjust the dielectric height and the trace thickness until you achieve your desired trace width. Make sure that the impedance does not vary too much when you change the above values.
How to calculate differential impedance:
Enter the differential impedance you want, the trace width, the dielectric height, the dielectric constant, and the trace thickness, and click the “Calculate Trace” button to get the accurate trace width. If you want a specific trace width and separation, you can play around with different values in the calculator until you achieve it. Make sure that the impedance does not vary too much, it can be +/- 2%.
Note that, in both cases, Sierra’s Stackup team does not check the odd mode impedance, the even mode impedance, the propagation delay, the inductance, or the capacitance because most boards only require one or two types of impedance: single-ended and differential.
Altium Designer, OrCAD and Allegro tutorials
How to set up differential pairs in the old and in the new Altium Designer (2015)
How to create a differential pair in Cadence OrCAD and Allegro