Key Aspects of DFM for HDI PCBs

Design for manufacturability (DFM) for HDI PCBs refers to designing layouts that reduce the errors associated with fabrication and assembly.

Before fabrication, the manufacturer will run a set of checks on the board files (Gerbers or ODB++) to confirm that these files do not violate the manufacturing constraints such as trace-to-trace distance, via diameter, annular ring diameter, etc. It is necessary to know the manufacturing rules to avoid discrepancies between the manufacturer and the designer. Let’s find out the potential DFM challenges and possible solutions to manufacture HDI boards.

What is HDI DFM process?

DFM ensures a set of design guidelines is followed so that the board can be easily manufactured without rising any issues during fabrication. In HDI, there can be a few design challenges as listed below:

1. Space constraints due to the increasing number of signals, component density, number of pins, etc. limit the space available for routing the traces.
2. Routing becomes difficult as the available space between pads reduces.
3. Manufacturing of boards becomes hard with the increasing layer count. Every additional layer tightens the stack-up registration requirements that result in a high board cost and low yield.
4. Due to the small component footprint and pitch, it is not feasible to use standard techniques to adjust within the required space.

HDI PCB Design Guide

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What's Inside:

• Planning your stack-up and microvia structure
• Choosing the right materials
• Signal integrity and controlled impedance in HDI
• Manufacturing considerations for higher yields

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A simple solution to these problems is to minimize the parameters of the interconnects to free up more space. As a result, more routing channels can be added to the available space. It reduces the number of required layers and also improves routing flexibility.

What are the routing constraints for HDI PCBs to pass DFM?

To optimize the HDI routing, there should be an emphasis on the reduction of trace width, via diameter, and via height. Let’s explore the design for manufacturing aspects for HDI boards in detail:

Traces and spacing

For HDI boards, PCB designers focus on reducing trace width to free up space. With thinner traces and smaller spacing, more routing channels can be accommodated. Even so, this induces problems associated with imaging resolution and etching errors. Read case study on designing an HDI board with 0.4 and 0.65mm BGAs to know how we overcame the challenges of placing multiple BGAs in an HDI board.

Imaging resolution

Image resolution describes how sharp features appear after exposure to a light source. With higher resolution, vital details are visible. Liquid photo-imaging (LPI) can only accommodate trace widths up to 4 mils since it lacks the required resolution and registration precision.

To solve this issue, PCB manufacturers opt for laser direct imaging (LDI). LDI uses a computer-controlled laser beam for imaging. It also accommodates dimensional changes for a precise image pattern. It offers benefits due to high photon density that leads to a better resist cure and less etchant seepage.

Based on the above considerations, it is advisable to shift from LPI to LDI.

Undercut during etching

During the etch-down process, cross-sections of traces become distorted as the trace width is reduced. Chemical etching etches downward as well as horizontally, so the final cross-sections are trapezoidal instead of rectangular. Copper thickness affects the time required to etch down the substrate. The thicker the copper, the larger will be the under etch. Smaller trace widths are significantly affected by the difference between trapezoidal and square cross-sections. However, this is not a problem with larger trace widths.

To resolve this, manufacturers can use thin copper weights such as ½ oz, ⅓ oz, ¼ oz, etc. It will reduce the undercut to a suitable level. It is also feasible to etch down the standard copper weight to the intended limit.

Contamination

Contamination is an important attribute to consider during DFM for HDI PCBs. As the size of traces decreases, the probability of contamination due to foreign objects such as dust, hair, etc., tends to increase. When the trace width reduces to 1 mil, small contaminants can occupy the space of the trace and can result in voids, or may even break the trace.

To mitigate this effect, it is recommended to use a class 100 cleanroom as defined by the ISO 14644-1. Cleanrooms are enclosed spaces designed to reduce particulate contamination and control other environmental factors, such as temperature, humidity, and pressure. However, it increases the cost and lead-time of the boards.

See our article, why we perform PCB ionic contamination analysis.

Via diameter and routing

Via size decrement can happen either by using a small drill or by decreasing the width of the annular ring. Additionally, minimizing the routing from the pad to the via can save space. Board designers can focus on reducing via diameter to enhance routing. Recommended drill size is 3-6 mils while considering DFM for HDI PCBs.

• For thicker boards, the diameter is > 6 mils.
• For class 3:
  • Minimum of 8 mils diameter
  • Minimum size of an annular ring is 4 mils

Drilling

Smaller via diameter can be achieved through mechanical drilling. But when the via diameter falls below 6 mils, the drill bit loses strength to withstand the cutting forces. Considering this, it is a better idea to use laser drilling. In HDI, microvias require precise controlled depth drilling. Such precision is only possible with lasers. The size of the microvias depends on the thickness of the dielectric between which microvias are implemented. Typically, the drill size is 1.3 times the dielectric thickness. For example, if the dielectric thickness is 3 mil, then the drill size will be 3.9 or 4 mils. This process has certain obstacles like aspect ratio constraint, the thickness of the dielectric, and material selection. See our case study on designing 8- and 14-layer HDI PCBs with stacked vias to know how we optimized the drill size and dielectric thickness to achieve the right aspect ratio.

Aspect ratio constraint

Aspect ratio represents how effectively copper can be plated inside holes (vias). Plating the interior areas of holes with copper becomes difficult with a smaller diameter and a deeper hole. To accomplish this, a plating bath with a higher throwing power is required so the liquid can gush into the minute holes. Microvias typically have an aspect ratio of 0.75:1. Drilling a 2 mil hole is problematic since it will be difficult to plate. It is one of the crucial points in design for manufacturing for HDI.

Quality of the hole

The dielectric material affects the hole quality. It must be laser-drillable. The procedure of removing material from a surface using a laser beam is called laser ablation. The reinforcement weave has a different ablation rate than the resin (FR4). Laser drilling removes varying amounts of material that results in poor hole quality.

In DFM for HDI PCBs, special attention should be provided to the uniformity of material. Some manufacturers customize the dielectric to reduce the spacing between weave fibers, which leads to consistent cross-sections. Non-woven reinforcement materials like PTFE, aramid fiber, etc., can also be used.

Material thickness

For maintaining the proper aspect ratio, the material thickness should be reduced. Use of standard prepreg or core material reduces material thickness. But, there is also the restriction on the lower limit for thin standard material. Reinforced material obstructs the shrinking thickness. The standard board dielectric consists of epoxy resin embedded with reinforcing material. The effectiveness of a reinforcer decreases as it becomes thinner. It poses challenges as the thickness of the dielectric drops down to 3 mils.

If very thin material is to be used, then non-reinforced material (1 mil thickness) is a good alternative. Some potential options are available that include epoxy liquid, polyamide, and resin-coated copper (RCC). However, these materials get affected with thermal deviations as their coefficient of thermal expansion (CTE) is less than reinforced materials. Therefore, thermal deviations should be minimal in manufacturing.

Significance of via-in-pad for HDI PCBs

Microvias can be connected to traces using dogbone or via-in-pad routing. Dogbone routing involves placing a via offset from the pad and connecting it with a minimum length trace. It loses effectiveness with the decreasing pad pitch. As a result, routing flexibility is limited since the trace and vias block the outer layers.

Via-in-pads allow immediate signal escape because they are placed inside component pads. As a result, the escape trace is removed, and more space is available for routing. It is the best way for routing but, it still has its downsides such as additional cost, long lead-time, etc.

Via-in-pads routing requires the PCB manufacturer to create and fill extra vias, adding new steps to the fabrication process, including drilling additional holes and plating vias with copper. These extra steps add extra cost. Also, vias have to be filled with non-conductive epoxy that is more expensive. As a result, lead-time will be more.

Via height

It is possible to improve routing flexibility by arranging the vias so that they only connect the required layers. Decreasing the via height poses some challenges in design for manufacturing for HDI boards.

 Blind vias

Blind via connects the external layers of the PCB to its internal layers without passing through the entire board. These vias can be drilled mechanically as well as using lasers. Through-hole vias are not feasible since it extends through the whole circuit board.

There is an aspect ratio constraint for blind vias too. At most, blind vias can connect three outer layers of a board. Additionally, it is affected by the lamination cycles that are influenced by the via structure. Generally, three lamination cycles are possible in HDI circuits. If it goes beyond that, it might create problems. In that case, managing via cycles is challenging. To avoid this issue, the designer needs to modify the structure of vias accordingly.

Another solution is to use buried vias through a sequential build-up process. It is the most flexible approach for routing.

Via layer connection

Via layer connection is a difficult task in HDI boards. They can either be stacked or staggered to build up the long connection. Due to the small size of stacked vias, voids can form while drilling. However, staggered vias will solve this issue. You can read our blog article design and manufacture of staggered and stacked vias in PCBs to know more.

Any layer interconnect structure is the advanced approach in HDI technology. It only uses microvias for the sequential build-up. The process provides maximum flexibility in terms of via depth and layer connection.

DFM for HDI PCBs in defense and avionics

HDI has many applications in defense and avionics that include communication equipment, control system, instrumentation, monitoring equipment, etc.

To ensure the proper functioning and transmission of signals, verifying DFM for HDI PCBs is crucial. The above-mentioned parameters related to traces, via height, and via diameter are necessary. Moreover, there should be an emphasis on the following factors while manufacturing HDI boards for defense and avionics.

Choosing a material

• Choose the heat-resistant materials as indicated by the glass transition temperature (Tg). The Tg value of the material should be high (200°C and above).
• Select a material that can work above the Tg but below the decomposition temperature (Td).
• Pick a material with a low dielectric constant (Dk) value.
• Opt for a material with high thermal conductivity.
• Pick vibration, shock, humidity, and radiation-resistant material.

Also read, how vibrations in space vehicles affect PCBA.

Temperature variations also influence material selection. Furthermore, factors such as thermal interfaces, design considerations, etc., are vital while considering PCBAs for aerospace thermal control.

Appropriate surface finish

ENIG: IPC-4552 recommends ENIG for HDI PCBs with BGAs of a very fine pitch because of its planarity and homogeneity.

ENEPIG: Provides better shear strength for SMT.

Laser drilling

• Laser drilling improves the efficiency and ease of drilling microvias, blind holes, and buried holes.
• It can drill a hole of a minimum diameter of 4 mils (0.004”) with precision.
• It facilitates the removal of carbonization from holes and ensures reliable plating.

Annular ring criteria

• An annular ring should be at least 0.05mm (2 mils).
• For external annular rings, a minimum of 20% reduction is permitted in the isolated area caused by defects.
• For internal annular rings, a 25μm reduction in isolated areas caused by pits, nicks, pinholes, or dents is permissible.

Negative and positive etchback

• In negative etchback, a protective layer is applied selectively before etching away the exposed copper. It is not suitable for military and aerospace applications as the connection established is not strong enough.
• In positive etchback, copper is applied and selectively etched. It provides a reliable three-point connection as shown below.

There are several compliance standards related to defense and avionics that have to be met to satisfy the conformance criteria.

1. IPC class 3/A: Military and avionics standard
2. AS9100D: Quality management standard for the aerospace industry
3. MIL-PRF-55110: Military performance specification for rigid PCBs
4. MIL-PRF-31032: Military standard for performance and conformance requirement
5. MIL-PRF-50884: Military standard for flexible or rigid-flex board

At Sierra Circuits, we adhere to all these standards, along with the necessary documentation required for compliance.

If you would like further clarifications regarding DFM for HDI, then please reach out to us in the comments section. Let us know what more you would like to see on our site. For more details regarding military and aerospace boards, download our design guide.

IPC Class 3 Design Guide

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What's Inside:

• IPC guidelines for manufacturing defects
• IPC standards for assembly processes
• Common differences between the classes
• IPC documents to set the level of acceptance criteria

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