Lamination Voids and Delamination in PCB Manufacturing

Lamination voids refer to the absence of epoxy resin in a circuit board. This can be detected while observing a cross-sectional area of a board with a microscope. 

A detailed understanding of voids, their root causes, and their prevention methods will help in manufacturing high-quality PCBs. There are different types of voids found in a circuit board – plating voids, ring voids, wedge voids, etc., but in this article we focus on lamination voids, their causes, effects, and resin starvation.

What is lamination void in PCB manufacturing?

The absence of resin at the interface of bonding materials results in voids during the lamination of a board stack-up. In some cases, lamination voids occur due to basic raw materials also. The delamination process between the dielectric and copper foil leads to foil cracks in the inner layers.

What is delamination in circuit boards?

When corrosive media have direct access to a metal substrate, then electrochemical reactions happen at the metal-coating interface in the presence of water, causing delamination. Delamination refers to the loss of coating adhesion to a surface or between coating layers. 

Delamination between dielectric and copper foils leads to foil cracks and barrel cracks. When stress is generated on the substrate, the through-holes resist the change, but as a consequence, this resistance causes barrel cracks in the board.

What causes lamination voids?

• In some cases, the CTE (coefficient of thermal expansion) of different materials like glass and resin doesn’t match.  When pressure is applied to a substrate, its CTE rises above the specified glass transition temperature (Tg). Stress on the plated through-holes occurs due to strain on the z-axis.
• The prepregs are not from the same family.
• Incorrect orientations. The prepregs and the cores’ grain direction should be aligned. Resin substrates are anisotropic, i.e. they have different measurement values in different directions (identify the warp and weft directions).
• Lamination parameters like vacuum, temperature, and pressure (computed w.r.t. to Tg of the material) are wrongly calculated.
• Profile of the lamination varies with respect to the environmental condition as well as the machine parameters. Therefore, before starting the process the profile must be set. 
• Wrong drill values.
• With respect to the design of the circuitry, if the copper is not distributed uniformly then there will be resin recession. Hence, you need to add sufficient copper thievings (the unwanted area of the circuitry) to balance the copper. To know more, read our blog balanced copper distribution and copper weight in PCBs.

PCB Material Design Guide

9 Chapters - 30 Pages - 40 Minute Read

What's Inside:

• Basic properties of the dielectric material to be considered
• Signal loss in PCB substrates
• Copper foil selection
• Key considerations for choosing PCB materials

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Effects of voids on a board

• To study the effect of voids, void shape, and void size, consider void distribution within the critical volume.
• Barrel cracks and foil cracks are responsible for improper lamination. If the crack appears on the knee position of the hole, a micro-section analysis is required to detect it.
• At the interface of adhesive effects, lamination voids affect thermal transfer, bond strength, and stress decoupling.
• Since voids hinder heat flow from the board to the heat sink, it results in temperature fluctuations and reduced adhesive strength.

How to reduce lamination voids

• Increase the average resin pressure through the use of larger consolidation forces or restrict the resin flow to minimize the pressure gradient.
  • Increase resin outflow from the laminate to facilitate the removal of mobile voids. The reduced cure pressures create an environment conducive to the formation of voids. In case of low cure pressures, you can restrict the resin flow and increase the average resin pressure in the laminate. You can facilitate resin outflow such that the voids can be removed from the laminate with the resin.
• Restricting the laminate resin flow causes the average characteristic void diameter to decrease from 200μm to 166μm while the void content increased from 5.5% to 7.3%. 
• Void content increases with increasing air escape path length. Since the voids are pockets of air entrapped during lamination, the best way to minimize the void formation at low lamination pressures is to stack/press the laminate in vacuum.
• The void ratio increases as the board lamination size increases. This is because of the longer air escape path length. 

Crazing and resin starvation

During the lamination, the resin flows out to fill the voids in the adjacent layers. When this flow occurs, the glass fibers will come in contact with the copper layers if there is no sufficient amount of resin in the prepreg. It is referred to as resin starvation.

The dielectric might break down since the glass has a lower dielectric breakdown threshold than the resin. Also, air-filled bubbles occur if there isn’t enough resin to fill the voids in the adjacent copper layers.

Furthermore, when the drill goes through these bubbles, chemicals can get trapped within them and can lead to the degradation of plated through-holes. If enough resin is not available to bear the stresses during drilling, then the glass fibers will start getting microfractures, leading to cathodic anodic filamentation (CAF). It is also known as crazing.

The majority of actual CAF growth is due to accelerated humidity and temperature testing conditions. It can be easily traced back to a lack of resin covering the glass.

Glass stop occurs when there is insufficient resin to cover the etched copper, roughness, and glass. It paves a pre-existing way for moisture ingress in a humid environment under applied voltage bias leading to CAF growth and failure.

Read our post on 6 types of electronic component failures in PCBs to understand various defects like CAF, brittle fractures, warpage, etc.

Eliminating voids at interfaces will increase the quality of laminated composite structures. The reduction in void ratio causes an increase in adhesive shear strength and a decrease in laminate thermal resistance. These critical metrics help to enhance component reliability and greater electronic performance.

Let us know in the comment section if you have any questions regarding lamination voids. Refer to our DFM guide to learn the design for manufacturing aspects. 

Design for Manufacturing Handbook

10 Chapters - 40 Pages - 45 Minute Read

What's Inside:

• Annular rings: avoid drill breakouts
• Vias: optimize your design
• Trace width and space: follow the best practices
• Solder mask and silkscreen: get the must-knows

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