Power Integrity, PDN, and Decoupling Capacitors

<h1>Power Integrity, PDN, and Decoupling Capacitors</h1> post thumbnail image

The continual silicon scaling has caused EM to become an increasing design factor in systems that depend on current generation ICs. Power plane noise is a significant source of signal integrity issues. The technological advances have succeeded in integrating over a billion transistors on a single chip. But the scaling of transistors has led to problems related to power distribution network (PDN). Power integrity is an important attribute in the next-gen high-speed digital designs. Not just for high power application-specific integrated circuits (ASICS), even clocks and SerDes are sensitive to µV of noise. On the other hand, high-speed logic gates can create high-frequency noise using just a few transistors.

The chip, the package, the PCB, and the VRM contribute to the generation power supply noise. Power supply noise is also generated due to core and input-output switching. The voltage fluctuations on the power supply rails of the transistors cause increased jitter and reduction in the voltage margin. These fluctuations have a direct influence on the operating frequency.

The speed of signals between ICs off-chip has steadily increased well above 112Gbps. The silicon industry is developing a technology that will aid a speed greater than 1Tbps between ICs. For instance, in 2.5D and 3D integration, the ICs are segmented. The communication between them is through interposers or the ICs are stacked on one another utilizing silicon vias.

The speed of communication between ICs determines the speed of the system. Hence the interconnection and packages play a vital role in deciding the performance of the overall system.

What do you mean by high-speed signals?

Many designers consider signals that are 50MHz and above as high-speed. It depends on the edge speed – rise and fall time of a signal.  We can generate 10GHz noise with a 1kHz repetition rate of our TDR generator.  It is all about edge speed. In other words, the frequency of a signal above which a PCB can significantly degrade circuit performance is termed as high speed. The PCB design process that takes into account the speed of the signal is defined as a high speed or complex board. For example, motherboards, routers, and smartphones.

What is noise?

It is something that tends to obscure a signal that we are hoping to see. The unwanted signal is defined as noise. Anything that we don’t want in a signal is termed as noise.

Power supply noise

Original signal superimposed with noise. Image credit: reviseomatic.org

  • Power supply noise
  • Simultaneous switching noise

Power distribution networks are usually associated with parasitics. The parasitics we are talking about here are resistance and inductance. Each time the circuit switches these parasitics generate noise between Vdd and ground nodes of the transistor level circuit. This is referred to as power supply noise. This noise propagates through the traces and it picks up reflections and cross talk along its way. When the signal reaches the receiver, it will consist of the originally intended signal with noise and cross-talk embedded in it. Designers should set a noise budget so that you have a predefined level of noise that can be tolerated in the circuit.

What is power integrity?

Power integrity (PI) is basically getting the appropriate power to the load from the input source. To be more specific, it is all about delivering clean power to the transistors present on the die of an IC. PI is the quality of power delivered to the circuits present on the die.

A die is the actual silicon chip found inside the package. The die sits on the package; the package sits on the printed circuit board.

In the electronics industry, power integrity is the analysis of how effectively power is converted and delivered from the source to the load within a system. Noise is generated at both ends (the source and the load). The VRM contributes noise as does the “load” and of course, anything else on the board can also contribute noise via crosstalk. Design for power integrity is nothing but managing the power supply noise. Managing the power supply noise across the voltage and ground terminals of the transistors, so that they function at high speed is called design for power integrity.

Power integrity means making sure all the circuits and devices are supplied with the appropriate power so that the desired performance of the circuit is achieved. It is not just keeping voltages within the allowed limits. Most of the circuitry in a device is dedicated to its power system. Steve Sandler says, “Today’s smartphones have 50 to 80% of the circuitry dedicated to its power system.” Hence designing a good PDN becomes a primary aspect.

We categorize networks fundamentally into two kinds:

  1. Signal integrity: Here we focus on all the interconnects. Transmission lines. Rely on Spice software of simulation. Parameters that we are interested in here are the Reflections and Rise time at the output of the driver.
  2. Power distribution network: It’s a standalone entity. Parameters that we are interested in here is the target impedance. According to Steve Sandler, “target impedance doesn’t work unless the impedance is also flat. Signal integrity causes power integrity and power integrity causes signal integrity.”

What is power distribution network (PDN)? (power and ground distribution system)

A power distribution system consists of a power supply, a load, and interconnect lines (transmission lines).

The design of the power and ground distribution networks has become a challenging task with the miniaturization on integrated circuits. These challenges arise from shorter transition times, lower noise margins, higher currents, and increased current densities. In addition to this, the power supply voltage has decreased in order to lower dynamic power dissipation. The increase in the number of transistors surges the total current drawn from the power delivery network. Simultaneously, the higher switching speed of these transistors produces faster and larger current transients in the power distribution network.

The fluctuations in the supply voltages are referred to as power supply noise. The power distribution noise at the terminals of the load should be maintained within the maximum allowed voltage fluctuations to ensure the correct operation of the overall system. The power distribution system should be carefully designed, supplying sufficient current to each transistor.

The power is delivered through a power distribution network which consists of passive components and interconnects from source to load.

PDN deals with the power and ground that are implemented throughout a design. It consists of several sub-systems like IC, package, and PCB. The IC PDN will have the fastest operating frequencies and signal switching, whereas, the PCB PDN will have slower signalling.

Designers specify power supplies, voltage regulator modules, capacitors, resistors, and inductors to improve the PDN’s performance. Poorly designed PDNs cause higher power dissipation (less battery life), increased noise throughout the system potentially causing functional failures. Poor design also reduces the performance due to slower signal rise/fall times.

If only the direct current (DC) is taken into consideration, then ohm’s (P = I2R) will assist in reducing the power dissipation. As it is difficult to reduce the operating voltage and the required current, we can focus on reducing the resistance. As a result, this will reduce the power dissipation. But since we are utilizing alternating current (AC current) we must consider the frequency range. Hence, rather than resistance (R), impedance (Z) must be taken into consideration during the design process. In AC analysis, much like DC/resistance, lowering the impedance as low as feasible is the goal for reducing the anomalies.

The power supply noise is a transient phenomenon that occurs due to the rapid switching of transistors. The design of PDN is best accomplished in the frequency domain. It is optimized to meet the target impedance value.

The objective of the design process is to ensure that the PDN response never exceeds the target impedance over the frequency bandwidth of interest. However, Xilinx allows 5% for operational voltage range, but only 10mV for noise since the noise gets into the PLL.

Managing Power Integrity

There are two kinds of circuits to be considered while working with high-level design.

  1. The core circuits:

The transistor-level circuits that communicate within a die.

  1. Input/output circuits:

Here the communication is between transistors located on two different dies.

Designing end-user products require design teams to spend significant effort on planning an effective EM strategy that starts with collaboration on the IC’s and system’s Power Distribution Network (PDN).

Designers always work toward increasing the operating frequency of their ICs. By reducing the power supply noise the operating frequency of an IC can be increased. The implication made here is that modifying the power distribution network has a direct effect on the operating frequency of the IC. Hence, designing an efficient PDN is critical for high-speed signals.

  • Poor power distribution will create signal integrity problems.
  • Poor signal integrity will hamper the power distribution network.
  • Signal and power influence one another. They are tightly linked to each other.

What is target impedance?

Target impedance represents the upper limit on PDN impedance that should be maintained in a system such that the power supply noise doesn’t exceed a maximum value. The power supply noise shouldn’t exceed the target impedance.

Impedance is a function of resistance, capacitance, and inductance and varies over frequency. The target impedance is defined by ohm’s law.

ZT = (VDD x Ripple)/ ( 50% x Imax)

  • VDD = supply voltage
  • Ripple is the percentage of supply voltage (VDD) that the transistors can tolerate without failure.
  • Imax is calculated from power and voltage.
  • 50% is the fudge factor representing an average current.

This ZT is a frequency-dependent parameter since the current drawn Imax can also change as a function of frequency.

As discussed in the earlier section, the goal is to lower the impedance to a feasible value while designing a PDN. Lowering impedance requires a target impedance and determining where the anti-resonance occurs.

Designers include capacitors when the antiresonance impedances are above the target impedance (Z). These capacitors will lower the impedance at that particular frequency without affecting the PDN’s performance. The addition of capacitors will, in turn, raise the cost of the product. If the antiresonance is lower than the target impedance then no action is required.

Here’s an article about ultra-low impedance testing by Steve Sandler that might suit your interest, “Ultra-low Impedance Testing Using the 2-Port Shunt-Through Measurement Technique.

What are decoupling capacitors?

Decoupling capacitors are quite frequently implemented to reduce the impedance of a power distribution network and provide the required charge to the switching circuits, lowering the power supply noise.

Decoupling capacitors provide the required charge in a timely manner and reduce the output impedance of the overall PDN. Practically, a decoupling capacitor is only effective over a particular frequency range. The impedance of a practical decoupling capacitor decreases linearly with the decrease in frequency and increases with the increase in frequency. This increase in the impedance of a practical decoupling capacitor is due to the parasitic inductance of the decoupling capacitor. The impedance of a decoupling capacitor reaches the minimum impedance at the frequency ω =1 √LC. This frequency is known as the resonant frequency of a decoupling capacitor.

An ideal power supply:

  • Would supply consistent voltage to the load
  • Doesn’t allow propagation of AC noise from the load
  • Has 0 ohms AC impedance between power and ground

Decoupling capacitors are used to keep the power rail transient voltages within allowable limits.

Two distinct goals that these capacitors serve are:

  • Charge supply: They allow local charge supply. They are considered as charge reservoirs. Circuits operating at higher switching speeds will have quick access to the charge reservoir to draw the required current. Decoupling capacitors an effective way to provide the required charge to a switching current load within a short period of time.
  • Filtering: The noise due to the switching of the transistors will be shunted to ground.

Decoupling capacitors reduce the Vdd core noise but occasionally improves the cavity noise generated by high bandwidth signals.

What’s the difference between signal integrity and power integrity?

Signal integrity and power integrity are closely related to each other but are also two independent things.

Signal integrity (SI) is the measurement of the quality of an electrical signal typically in an electronic printed circuit board. A stream of binary values is represented by a voltage (or current) waveform in a digital system. But in a practical sense, digital signals are fundamentally analog in nature, and all signals are subject to effects such as noise, distortion, and loss.

Comparing SI and PI

SI PI
Analysis based on Transmission lines Transmission planes
Typical Impedance

Targets

Around 50 Ohms impedance level match In mili Ohms (generally do not have defined impedance to match)
Subset of Analysis We look for signal quality We look for Impedance, DC Drop, Decoupling, Noise impacts
Models needed IBIS, SPICE ADS, Capacitors with Parasitics
PCB Design changes Driven Trace width, Length, Spacing Terminations Amount of metal to carry current,

Number/Value/Mounting of Caps,

Power/Ground Plane Pairs, Stackup

How to measure power integrity?

Common Power Integrity Measurements

  • PARD (Periodic and Random Disturbances): noise, ripple (Vpp), transients—It is the deviation of the DC output from its average values with all other parameters constant. It is a measure of the undesirable AC and noise components that remain in the DC output after the regulation and filtering circuitry.
  • Static and dynamic load response- It is a measure of the supply’s ability to remain within specified output limits for a predetermined load.
  • Supply drift- PARD like variations occurring below 20Hz are referred to as drift.

HyperLynx

Another tool used by designers is the HyperLynx – Power Integrity tool.

This tool identifies potential power integrity distribution issues and predicts what can interfere with board design logic. The tool helps in analyzing the board at an earlier stage of the design cycle and gives an idea of how your circuits will behave.

HyperLynx is integrated with Mentor’s Xpedition and PADS Professional flows and also works with all major PCB layout systems.

Keysight Advanced Design System (ADS)

PIPro provides power integrity analysis of PDN, including DC IR drop analysis, AC impedance analysis and power plane resonance analysis. PIPro utilizes a common setup and analysis environment within ADS. It’s more general purpose since it can include analog, power, RF, and µWave simultaneously.

Return Path Discontinuities

Signal lines are always routed in the presence of a power distribution plane. The power distribution planes serve as the path for the return currents of the signal lines. Any discontinuities in the current return path can affect signal integrity.

Both in a package and a printed circuit board, interconnects are always routed in the presence of voltage and ground planes. Any discontinuities in the current return path will cause an issue with the speed of the traversing signal.

Unless you comprehend the current loops in your system and the discontinuities associated with it, it is hard to predict the return path discontinuities and their effect on the signal integrity of the waveform.

Return path discontinuities

In PCBs normally we have reference planes that are either connected to the power or ground of the driver. When the signal and return currents are in phase, their magnetic fields cancel out each other. When they are out of phase, the magnetic fields don’t cancel out very well and hence create problems (radiated emissions).

The return path discontinuities (at via locations) are either mitigated by capacitors or by stitching the planes together using vias considering the planes are at the same DC potential. This design approach provides the necessary continuity for the return currents and improves the channel response. Decoupling capacitors reduce the jitter. Embedded decoupling capacitors and thin dielectrics are now commercially available for improving signal and power integrity.

Note: Stitching vias provide return path continuity when signals travel through different layers and planes. Never route high-speed signals across a break in the reference plane.

Conclusion

With the increasing complexity of PCBs and packages, managing PI and SI is quite challenging. Implementing more and more decoupling capacitors in PCBs and packages isn’t the right solution.

We would like to thank Steve Sandler for sharing his insights and making this article more informative.

Not only is Steve the founder and CEO of Picotest but he is also THE rock star in the field of power integrity. He has been involved with power system engineering for nearly 40 years. He frequently lectures and leads workshops internationally on the topics of power, PDN, and distributed systems and is a Keysight certified expert for EDA software. Just in case you didn’t know that already…

If you require high fidelity testing and measurement tools for power-related applications, you will find everything you need on the Picotest website.

We are happy to have a power integrity expert by our side. Thank you, Steve!

Articles by Steve Sandler:

Designing Power for Sensitive Circuits

PerfectPulse Is the Pocket-Sized TDR Every Engineer Needs

2 thoughts on “

Power Integrity, PDN, and Decoupling Capacitors

  1. Shashank says:

    Hello there,
    I have doubt in the Decoupling capacitor section about the following sentence.
    “The impedance of a practical decoupling capacitor decreases linearly with the decrease in frequency and increases with the increase in frequency.”
    Is that correct? I am referring the following picture here. Where it is other way. ?
    https://electronics.stackexchange.com/questions/3879/frequency-dependence-of-electrolytic-capacitors/3887

    Please help understand.

    1. Rahul Shashikanth says:

      Hi Shashank,

      The statement mentioned in the article about the decoupling capacitors is precise. Here the capacitors are assumed to be made up of ceramic dielectrics. If you consider decoupling capacitors made up of other materials like plastic film or paper, then at high frequencies they would breakdown. Hope this helps.

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