Nitin Bhagwath: The HyperLynx Expert
Nitin Bhagwath sat with us at DesignCon 2019 to discuss Mentor Graphics and HyperLynx. From simulation to reality, here is how the PCB software tool works.
Nitin Bhagwath – The Interview
Here are the topics covered in the interview:
- 0:08 What was your DesignCon paper about?
- 3:57 Can you tell us more about HyperLynx in this scenario?
- 4:46 What kind of information does HyperLynx need to effectively run?
- 5:41 There’s no change from simulation to reality?
- 6:33 What are the assumptions that HyperLynx makes?
- 8:30 How do you handle surface roughness?
- 9:45 What area of HyperLynx do you focus on?
- 9:59 Are DDR-5 and DDR-6 groundbreakingly different from DDR-3 and DDR-4?
- 11:50 Can you discuss equalization?
- 12:30 What is the degradation in the channel?
- 13:03 So the PCB is the channel?
- 14:15 What advice would you give to people venturing in DDR-5?
What was your paper about this year at DesignCon?
The topic of my paper was about the interaction of power integrity with signal integrity. Many times what happens in any group, in any design team, is you have a power engineer and you have a signal integrity engineer and a design engineer. At DDR speeds, DDR4 and definitely DDR5, even some DDR3 speeds, the power integrity starts mattering to the signal integrity. So in the olden days you could just isolate these two effects, treat them separate and they would magically work. But now, we are starting to need to look at them as a combined whole.
There is two specific ways where this matters. Number one, the power noise – any noise on the power rail – gets propagated onto the buffers. The buffers, they assume that they can get an ideal power supply. So when a buffer suddenly tries to drive a signal and it doesn’t get the energy that it needs, the signal that it spits out might not be optimal. So when you have 72 signals trying to get power at the same time, you can see how if the power rail is not able to provide the power, these signals start getting a little bouncy. That’s called simultaneously switching noise due to simultaneously switching output. Because you got all these signals simultaneously switching are causing all this noise. This is an effect, it’s been around for a while, but it’s just that at DDR4, DDR5 speeds it becomes more important.
The second area where power and signal start interacting, which people many times don’t think about, but maybe should, is the return path.
When you have a signal, it’s not just electrons going, it’s actually an electromagnetic wave which has a signal and a reference. So you need to think about where the reference is. If you have an ideal ground plane and you have a signal traveling over it. No problem. You can assume a nice PCB transmission line and it goes on its way. But if you think you have a signal via, going from lets say the top layer to the bottom later, the question becomes, Where is the return path for the signal via? If you don’t have a close-by stitching via, so that it offers a nice return path for the signal via, you’re going to get all kinds of signal noise that you might not otherwise be able to find out what’s causing it.
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Furthermore, if you have multiple signal vias; so let’s say you have a DDR box and you have DQ0, DQ1, DQ2 and DQ3 all sharing one ground stitching via, they’re all coming back in the same localized area. That’s gonna cause cross talk. This is not trace-to-trace crosstalk which happens when you have two traces very close together. This is crosstalk because you have many signal vias sharing one common ground via.
With DDR this is more common than you might think. With srds what happens, even though srds also has very higher data rates, you often have a lot of eyes on it so that you make sure that you have good distinct stitching vias for every differential pair of signal via. But with DDR not so much. You don’t have the space. You have a lot of signals. So you have a whole bunch of signals just scatter shot on the PCB and you just put in as many ground stitching vias as possible. And sometimes that’s just not enough.
So you would need tools such as HyperLynx. So you can use HyperLynx to analyze this. DDR3 speeds not so important, but DDR4, DDR5 speeds you would definitely need a tool like HyperLynx to be able to figure out, is this good enough for you? So that when you get your board back you know that it’s going to reliably work.
That’s what the paper was about.
With HyperLynx I guess you can figure out your threshold or if you have enough stitching vias?
You can, yes. With HyperLynx, you would take a board that you have and you’d be able to figure out what the frequency domain response is, which will tell you where some resonances are. And you can address those specific frequencies. Maybe you would know some dimensions corresponding to those frequencies and be able to figure out where those dimensions are.
More likely, what’s going to happen is you’re going to have your eye diagram really closed. Then what you would do is you would say, let me try to repeat the same experiment, but assume ideal vias. And then suddenly, your eye diagram opens up. Then you know that it’s one of the vias that’s the problem. So then you can narrow down and try to figure out through various experiments where the problems actually are so that you can mitigate them, add more stitching vias as needed.
What information does HyperLynx need to effectively run?
To run HyperLynx, it’s actually very simple. One of our big things that we try to do is try to make it as easy as possible. Engineers are often proud people. They don’t want to admit things they don’t know. So that’s okay. We try to abstract everything away from what’s needed to things the engineer can absolutely provide. And as they have information, you can toss it in and do a Ph.D. level thesis. So the basic things you need is a board layout file. It doesn’t matter what format your board layout file is. You can use it.
Number two, you’re gonna need some kind of buffer models. If you have ICs on your board, the IC vendors website, you should be able to download it or send an email to the AE and they should be able to help you out. Those are the two main things. Once you have those two things, we take care of the rest. You don’t have to worry about anything else. And once you do that analysis, you know that your board is good or not.
So are you saying there’s no difference, there’s no change from simulation to reality there? Meaning if HyperLynx says, “Oh green, everything is good.” And then a real board is made, that everything is, should be good? There has to be a difference, otherwise these big Rohde & Schwarz and Tektronix, those guys wouldn’t exist.
There are actually three different things: simulation, measurement, and reality. There’s an old joke. It says, If you’re in the simulation environment, ecosystem, you always trust the oscilloscopes, the measurements. If you’re in the oscilloscope business, you always trust the simulations. Because simulations and oscilloscopes measurements have limitations. Garbage in – garbage out. With simulations, we’re making a lot of assumptions. And those assumptions, if they are wrong the output is wrong. When you’re making a measurement, how you make that probe, where you’re making the reference, a lot of those details matter a lot. If you’re making bad assumptions there, whatever you see on the scope is irrelevant. Because you’ve got this third thing, reality, that none of us can see.
That’s exactly what I’m asking. What are the assumptions that HyperLynx makes, that maybe as an engineer you don’t want it to make those and you should give that there?
Let me reframe that question. HyperLynx, to be honest, like any other simulation tool is based on physics. Physics hasn’t changed in the last decade. Even if we live in a new reality, physics hasn’t changed. But what assumptions you put into it matter. You can go down to quantum mechanics, which takes a supercomputer to analyze. Or you can make a lumped assumption. So you just have an RLC model, which analyzes quickly, but you’re making a really broad assumption.
Almost any simulation tool, definitely HyperLynx, you have the slider of how much assumptions the user makes. If the user wants a lumped system, just an RLC network, no problem. We’ll give it. If you want to go down to a really low level of accuracy, a high level of accuracy at a high frequency, we’ve got solutions for that too. So if you want to go up to tens of gigahertz, no problem. We’ve got solutions for that. But the data that’s provided for that has to be accurate.
So what are some of the data that you need to have?
You need to make sure that your board file is accurate, that the stack-up is accurate. That’s one of the first things that I’ve seen a lot of people make a mistake on. The stack-up that they provide is inaccurate because they haven’t … When they do the layout, they don’t put the stack-up information in. You got to make sure the IBIS models are accurate. That whoever created those IBIS models, they’ve done a good job of it. You’ve got to make sure that when you’re looking at a frequency plot, you’re looking at the frequency range that’s of interest to you.
Those are three things that have come to mind off the top of my head, but I’m sure that there are many more things. But the key things for these assumptions is it’s not HyperLynx’ assumptions. They are user assumptions. You got to make sure that the users provide the right information. Garbage in – garbage out. So as long as they’re providing the right information, physics is physics. It gives the right results.
Sierra manufactures circuit boards and there are two different types of copper on the circuit board. There’s electro-deposited copper from the material vendor and then there’s electrolytic plating that we do. And you can see in a cross-section the difference between the two platings.
And they have different grain structures.
Because of skin effect, do you only care about the outer copper grain structure? Or do you care about the full trace grain structure?
HyperLynx does model surface roughness. The question is, how do we model it? We have some standard models supported. If I had the 3D product manager here he’d be able to recite all of them and tell you the details about all of them. I know there’s a cannonball model and there is the Hammerschmidt model. There are some standard models for modeling surface roughness. So as long as the manufacturer provides the right values for those models, they fit in pretty well. If you’ve got a better model for modeling this surface roughness and the imperfections of the copper, it’s something we’d have to discuss.
So at some point, I’m making up a number, let’s say 20 gigahertz. This starts mattering for some distance. Let’s say at 40 gigahertz you found that this cannonball model isn’t good enough. If you’ve got a better one, that’s where places like DesignCon, we get to talk and figure out, Okay, let’s try to find out this new model. But, I don’t want to give any numbers. Easily, many tens of gigahertz, our models correspond to what we can actually measure pretty well. Of course, at the higher frequencies, we have to incorporate things like surface roughness.
So are DDR5 and DDR6 groundbreakingly different from DDR3 and DDR4?
Well DDR4 in its own way was groundbreaking with respect to DDR3. And DDR5 has its own, shall we use the euphemism, set of challenges that keep us in business and allow us to have jobs. The new things for DDR5 are that it’s going to have equalization built into the DRM. So this is new because memory is a very cost sensitive product. So putting equalization in memory is expensive in terms of silicone, cost, and power. But at the data rates that DDR5 and LPDDR5 are going, there needs to be some kind of equalization in the memory.
So the challenge now becomes, how do we analyze this in simulation? And even in the oscilloscopes, to be honest, because you can measure at the pin. You don’t have direct access to what’s happening after equalization. So these are new challenges, that we’re having these conferences, to try to find a good solution to.
What problem would you recommend scope vendors to solve for DDR memory?
The scope vendors and us, and all the simulation vendors, precisely for the question you asked earlier about how well they correspond to each other. We work together to try to make sure that our results match up. Because you have engineers who look at the results and say, “I want to see the simulation.” We see people who say, “I see the simulation, I want to see the results.” So we regularly work together to try to make sure that our results match up. So we’re largely in sync with what they’re thinking about.
And they’ve got the same problems, similar problems to what we have. Which is, for DDR5 how do we accurately make sure that when the chip receives a signal, that it’s going to work. So that is going to now involve equalization as well. So post-equalization, how do we make sure signals work? That’s what they’re thinking about.
Can you explain what post-equalization or equalization is?
That’s a very big question. Let’s see how I can make it easy. You have a transmitter.
Let me explain equalization. You have a transmitter, you have a channel, you have a receiver. The transmitter says something. The channel muffles it/ And the receiver hears something. Which may or may not be what the transmitter said. This channel, it does its job of trying to degrade the signal of the transmitter. Equalization tries to compensate for effects off this channel to try to make sure that the receiver receives what the transmitter said in the first place. There are may ways of doing it, but in a nutshell that’s all it is. It’s a way of offsetting the properties of the channel so that the receiver understands what the transmitter said.
How does the equalizer know what’s the degradation in the channel?
Great question. The equalizer doesn’t, but the person programming the equalizer does. So they will use simulation, they’ll use simulation like HyperLynx. They’re going to use scopes to try to find the properties of their channel. And try to program different equalization capabilities to try to see what works best. That question in itself is a big question. And how to optimize that, how to optimize the equalization to get the best result is a pretty big question in itself.
Got it. So PCBs are the channel? PCBs characterizing the material, characterizing the trace, that becomes important?
Absolutely, and that’s our business. So we have to take the PCB that’s provided and we have to model it as best as possible. It’s more than just the PCB though. You also have the package and you have the drive capabilities, the drive strengths. And at the receiver you have the loading of the receiver and the package there as well. And the termination of the receiver and so on. Plus, you have the power supply that we talked about earlier. So the PCB is a significant portion of the effects of signal integrity, but there’s a whole ecosystem that actually causes the full degradation of the signal. Everything really needs to be taken into account to make sure that you’re accurately modeling it.
To address your earlier questions about what assumptions are being made, you can ask yourself which parts of this ecosystem are you making assumptions about. For example, let’s say you have a termination and you’re just assuming it to be a ideal resistor. That’s an assumption. Is that good enough? Maybe yes, maybe no. Cause if you want a better model, it takes more simulation time. But if you assume a resistor, maybe it’s not accurate enough. So where you make that assumption trade off, that’s a part of the question for the engineer.
What advice would you give, other than saying to use HyperLynx, people venturing into the latest DDR technology so that they can be as successful as possible early on?
Right. So what advice would I give for people entering the DDR5 design? I would say more so than with DDR3 and DDR2 and DDR4 even, see with DDR2 and DDR3, rules of thumb have taken hold. There are grand old masters who know the business and they say, “Hey, do this and you’re going to be fine. Don’t worry about it.” The young ‘ens follow that advice. DDR5, more than previous generations, I would say you have to simulate with a tool like HyperLynx. There are other tools, but I would recommend HyperLynx. But even besides that, it’s about simulation. Because you don’t have physical access to where the actual receiver is making its decisions. And without knowing it, there’s a huge element of either hope or having a longer production cycle.Tags: DDR, DDR5, HyperLynx, mentor graphics