During DesignCon 2018, Sierra interviewed Heidi Barnes, Senior Applications Engineer at Keysight Technologies. We asked her questions about power integrity, capacitors, and impedance.
0:07 What are your thoughts on the trends in both the signal integrity and power integrity industry this year?
It was very interesting this year. Power integrity is something I’m getting a lot more involved with, working with Steve Sandler of Picotest, and it was exciting this year, we did a paper, co-authored a paper with Xilinx, and they have they 32-gigabit ultra-scale FPGA, and of course you worry about those really high-speed, high-frequency transients causing a lot of simultaneous switching noise, machine node noise… It turns out that when we actually got into this project and started investigating things, the package and the dye have a lot of decoupling that handles the high-frequency switching, the 32 gigabits.
What was more of a challenge was the in-between, where the voltage regulator model doesn’t cover, the control loop is no longer covering that frequency range, and before we get to the high frequency. So, it was the mid-range decoupling that was much more of a challenge, that has to handle the step load, sort of state change of turning transceivers on and off.
“From a very simplistic point of view, you need to look at the VRM.”
1:06 Are there any results or conclusion you can share?
From a very simplistic point of view, you need to look at the VRM. You can look at it from an on and off state to identify the active inductance of what frequency range the VRM can go up to, and then if you actually can get the package dye and S-parameter model from the FPGA or your load, this transceiver module, if you have that package dye model you have a pretty good estimate of what capacitance decoupling they have in there, in terms of if you look at the S-parameter impedance versus frequency, you’ll clearly see how much capacitance they have in that package. That tells you how much inductance you can have on your printed circuit board, and at what frequency range your capacitors have to go up to.
1:51 Are there any guidelines you can share with new PCB designers?
Some of the guidelines for a first time designer for power integrity is just selecting capacitors. The time-ten rule doesn’t work, the point-one microfarad, the one microfarad, the ten microfarad … If you actually do a simulation and look at trying to flatten out the impedance, you’ll find that there are some much better choices for the capacitor values. If you design for flat impedance over frequency, it actually works out to be the minimum numbers of capacitors to achieve the performance that you require.
Typically, unless somebody’s already used the process of course, you can reduce the number of capacitors if somebody’s just leveraging a previous design where they’ve done the factors of ten, you most definitely can reduce the number of capacitors.
The thing that is interesting to me with power integrity is that in the old days you used to sprinkle these decoupling capacitors around, but back then the currents were much lower, the devices were running slower, the transients were slower, and a lot of times you were just trying to really decouple some of the noise.
You’re decoupling capacitors now, you have to realize, they’re actually sourcing and syncing the power that your load needs, and that’s a much more difficult problem to make sure that they’re getting the right amount of power, when they need it.
“The VRM can no longer really keep up with the actual transients that the loads are doing”
3:15 Can we reduce the number of decoupling capacitors by this process?
Correct. The power that you need at the transient frequencies, the DIDT of the load… We’re no longer seeing a steady-state, low frequency power delivery. The VRM can no longer really keep up with the actual transients that the loads are doing, and so that’s why the designer’s job of designing that mid-range decoupling is very important.
3:41 Does one need to have a reasonable idea of the power requirements at different frequencies?
Again, as you just mentioned, having the requirements of the power at different frequencies is what every designer really wants, but, like most of the engineering world, you can’t always get what you want, so you have to work with what you can get, and with understanding what the current requirements are at different frequencies, one of the things that is interesting with high-speed digital, is because the digital pattern can vary so much, and have a lot of different spectral content, that’s why we talk so much about flat impedance, because we need to be flat across a broad range of frequencies, not just one.
And then, the other thing that’s interesting is, vendors don’t want to give you that very detailed spice-model of their product, so again it’s very difficult to get that spectral content of the load, so in this case what we did with our paper this year with Xilinx, we looked at the package model and said: the package has a capacitor in there, they’re going to handle all the high frequency above that. So as long as I know what the basic step load is, and where their package frequencies will take over, I can estimate a rise time that gives me a good spectral content, and I can start playing with a step load to exercise my printed circuit board mid-range decoupling.
5:01 If your impedance is not flat, how does that affect signaling?
I worked with Steve Sandler of Picotest and he did a couple of years ago a great paper on rogue waves, and if your impedance is not flat, even if you’re below the target impedance, if you have some anti-resonances in there, at one of those frequencies, you’re below the target impedance and your ripple voltage will actually meet spec, but if you’re unlucky enough to excite one of those frequencies along with the two others, now it’s like a rogue wave in the ocean: you get one wave going and at the peak of the first frequency wave you start the higher frequency, and at the peak of that one you start the next higher one, and you can actually get an amplitude that’s much higher than just the single resonance, and then even though you’re underneath the target impedance, the addition of all of them on top of each other can exceed your limit.
It’s a rogue wave effect, and although it’s a low probability, I think we all saw the keynote speech this year on automobile safety, and when you start talking about very high volumes or very high usage of something, then the electronic reliability has to be very small, and so then these rogue waves can’t start to become a factor.
6:23 Any new developments in the measurement fields over the last year?
Well of course we all see the speeds just continue to increase: the 400-gigabit type applications, PAM4, they’re even talking 16-level amplitude modulation, so I think those are challenges that all the instrumentation are keeping up with. It’s very exciting for Keysight, because we have both simulation and measurement.
We’re launching sort of what we call a path-wave type of concept, where we’re really trying to integrate the software between instrumentation and measurement and the data transfer, and the data analysis, to really leverage all of that capability and make it much easier to use that information all the way from design to manufacturing and product life-cycle.
7:11 Is the PAM4 getting more traction?
You know, PAM4 is an interesting one. Every year we have people that say “it won’t work, it doesn’t make sense,” and now we have vendors selling PAM4 chips, so we have component vendors selling products that will connect all these PAM4 devices. So, I believe, maybe it won’t have the fast ramp of some other technologies, but it’s definitely here to fill some of the niche applications.
“The ground return is very significant for power integrity.”
7:33 Do you have any advice for PCB designers?
My advice for the printed circuit board manufacturers and designers is something I think I usually say in my interviews is, don’t forget about the ground-return. Ground is just as important as signal and I think that’s the worst thing that a lot of our schematics do; you pay attention to all your net listing of your signals, and ground is something off in the corner. It really is important how the ground return follows. Power integrity is a great example; you think you’re down at DC, it’s not AC, it’s not RF, not microwave, but the currents are so high, the impedance is so low that that ground-return inductance and a little bit of resistance there, it can actually start to impact, and ground return again is very significant for power integrity.
8:20 What’s your favorite part about this year’s DesignCon?
So my favorite thing about DesignCon is just getting a chance to see a lot of my friends that I only see once a year here at DesignCon; it’s an international conference so I see people from all around the world.
This year was exciting: we did a bootcamp, and I believe almost half of the people there were new to DesignCon, so a lot of new faces, and increased attendance and very relevant papers to the fast-changing technology of electronics.
8:47 Any advice for first timers attending DesignCon?
If you’re a first time attendee to DesignCon, it’s challenging; there’s a lot of activities going on. The first day, we have tutorials. If you’re first-time to DesignCon, take advantage of the bootcamps. The companies that do those, they’re putting a lot of effort into the basic training and they’re wonderful courses taught by the very top engineers in the field.
The other thing is, during the week, the papers from each of the tracts, you know, select a tract and then focus on that and get the full impact. The other thing that I love also, because I’m with Keysight Technologies, we do a special forum, Keysight does a special session that we sponsor. It’s free to attend and we also take a look at the latest technologies that are coming out.
So, there are a lot of opportunities, and of course the evening reception events and a lot opportunities to meet the speakers and authors of the papers.
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