Allegro, Sigrity, signal integrity, ODB++, IPC-2581… Dennis Nagle, Product Engineering Architect, told us all about the ECAD tools news at Cadence.
0:10 How is the Cadence development office related to the offices in the Valley?
So, the headquarters are obviously out here in San Jose, but from Cadence as a perspective as a worldwide company, we have a bunch of development offices all over the world. The office outside of Boston that I reside in is where Allegro was developed. I cut my teeth on Allegro for a lot of years, moved into the signal integrity space. So it’s a pretty exciting time for us having just acquired Sigrity and what not for the layout side of things.
0:41 What can you tell me about the history of Allegro?
Allegro is version 17.2 right now. When I started with what was Valid Logic Systems at the time, I started on Allegro 4.1.2, and it was a great release.
1:01 What is the latest on the signal integrity tools that are now cohabiting along with the Allegro design?
It’s funny you should ask about where we are lately with signal integrity tools with related to Allegro because it’s basically what I’ve done my entire career. When I started with Allegro, I started help develop the constraint management system, and the signal integrity tools were still not quite as popular, or as necessary as it is today, but we feel very strongly in tightly-integrated tools between layout and analysis. We realize that signal integrity designers would always want to use their core set of tools, but there’s always a communication and a collaboration issue where the person that needs to fix the design is in layout. So we’ve been providing tools that not only allow you to better communicate with your signal integrity or power integrity experts, we’ve also been providing better tools that you can run right within the layout.
Some of these tools won’t even require signal integrity models but they give you the same electrical quality that you would get from any signal integrity analysis. We’ve been integrating engines underneath the hood, and the other thing that we see in this area that’s going to be more important is even if it comes down to some kind of electrical check, those electrical checks are eventually going to have to be power aware.
2:12 Has the incorporation of signal integrity tools and infrastructure in an ECAD environment become almost a necessity?
Some level of integration of signal integrity tools into layout has become a necessity. You can always have separate disciplines, you can have your EEs just do the schematic. You can have a dedicated layout person and you can have your experts for analysis. No matter what, there has to be some level of communication between them. So, we’ve developed integration to the point where, say the expert runs the analysis, that report can be invoked from the layout tool. Now, they can cross-probe to where the violations are. We’ve even got it to the point where you can point to the set up environment that the expert ran and then re-run the analysis as many times as you want. It kind of shortens that fix, analyze, fix cycle and just makes it better.
3:00 Does Cadence also have a thermal simulation?
Yes, we do. We have new thermal simulation capabilities that will be coming out, but we have thermal co-simulation with our power integrity tools.
3:11 How do these Cadence tools compare with HyperLynx and related Mentor tools, especially when it comes to signal integrity?
That’s actually a great question. So if you’re looking for how our tools relate to other tools in the industry, the paper I gave at PCB West was about how designers could do better with things like impedance coupling and return path. I gave recommendations on what to do. The matter is that there’s a lot of other competent EDA tools out in the market place. Some of these other tools, though, tend to focus on more of like a point tool operation.
And again, they are all capable. We have them as well, we have people that run our tools as point tools with other layout systems. The difference is, I believe, that we bring a better level of integration to the market for your team. Your team will have a better collaboration and if you’ve got a layout team that wants to do more, wants to do more than just connecting traces, wants to be part of the ability to analyze and fix the design, we provide you those capabilities.
Some of the other things that we’ve been seeing in the industry, we see more EEs that are responsible for schematic and layout. Why should these people have to learn additional analysis tools? They’ve already learned two different environments. And they probably have dedicated signal integrity or power integrity experts that they can call upon, but we find that they would much rather do some of the lower level or first order signal integrity checks right within the layout tool. And those are the capabilities that we provide.
4:43 Most of the ECAD tools are basically based on a subtractive technology. What about tools for an additive technology?
That’s an excellent question. When you look at traditional PCB technology like that, which is more of a subtractive technology, I believe the additive was much more popular in the IC space. We’re already starting to see some of that bleed into the packaging space. Just recently I was asked to look at a design and they were having issues translating that package design to the analysis tools and I’m trying to look at both sides of this. I literally had to go and ask what is going on and they basically said “we are trying something new here.”
It’ll eventually. It’s going to be part of the natural evolution, I believe.
5:24 Has any attempt been done in Cadence to make a tool for additive technology?
No, we don’t have anything currently that would do any type of additive. I think what had happened, is if you look at the Allegro tools, in general, they’re very flexible. Think of it as certain cell phone technologies. One type of cell phone gives you one way to do everything. Another common technology is a little more flexible. We like to think of Allegro being in that latter camp. I remember someone quite famously saying to me, years ago, when someone calls and says “how do you do this?” It’s not like “oh, the tool was never designed to do that”, it’s like “let’s take a look, there’s got to be a way to do this”.
So, getting back to your new technology question, they were still able to do something, call it a workaround, we won’t quite call it a hack, but they were able to do something in the packaging tools to do that additive process.
6:20 What kind of workarounds would designers need to do in Allegro if they were working on a 1-mil trace and space technology?
If you were getting down to the dimension to where traces are at a mil, or vias are at that kind of size… From a design prospective, I’m not sure there would be anything that’s really different. From an analysis tools perspective, I could tell you’d probably want to go to a full wave, maybe even 3D full wave type of technology, but very confident we have those capabilities to analyze that kind of stuff.
Allegro should very easily be able to take care of 1-mil trace and space technology.
I feel like I’ve been saying it a lot. A lot of things just come down to trace geometries and material properties. And a lot of what you are going to do and make your life easier is if I’m designing a layout just for artwork purposes or just to do something for manufacturing, I just need to know what layers and just send it out. But if I’m going to do any type of analysis later on downstream, I’d want to make sure my stack-up has the right dimensions, has the right material properties. I mean for artwork no one cares what your thickness of your dielectric with the material was, but for any type of analysis, you better have that correct.
7:22 Does Cadence have some kind of a material database in its tools?
So, as far as high-speed materials go, it’s kind of interesting because since the acquisitions of Sigrity, we’ve just recently moved to a common materials file database.
In the Sigrity environment, you’re going to translate from the CAD system. If you look at any Sigrity work-flow, the first thing it’s going to tell you to do is to go check your stack-up. But sometimes what the translator will do is look for the best match. Then it’s up to you or your responsibility to go ahead and figure out, “oh that wasn’t really what I want” or to make sure that the material proprieties are correct. So now we actually share common materials database between the two tools, the two environments.
We feel very strongly in using the right materials and being able to model and give the user access to the type of materials that they’re using.
If a user wanted to integrate their own tools, the Allegro format was not all that flexible. The new format is all XML based. So it’d be much easier to transfer information.
And the other good thing about the new material file format is you can migrate your old file formats in Allegro to the new format very easily. It’s kind of like a merging process, so you’re not losing anything.
8:51 What about backward compatibility in Allegro in general?
I can tell you it’s gotten better. I’m only laughing because I’ve been with Allegro or with Cadence for so long. You have a major release come out and having a design database, you have to make changes to support either new technology, new functionality, new features. But, I know in the past it used to be generate manufacturing file formats, read in a new net list and try to get this thing synced up together again. But we have done better in recent years with putting more down rev capabilities. Now those down rev capabilities will sometimes strip out features or functionality, but we warn you what that is. It was a painful lesson for us to learn over the years, but we do have better down rev capabilities, now.
9:35 Anything on ODB++ and IPC-2581?
I might not be the best one to answer about ODB++ or IPC-2581. But we believe in standards. We don’t believe or like to have one vendor control such an important thing. I think the standard itself has taken off. It’s got a lot of good members in the consortium, and we have very big plans with what we can do, not only in the Allegro side, but with the analysis side. So we have some very new and exciting things that I can’t quite disclose right now but that will be happening in the signal integrity space.
Simple things I can talk about like doing better imports into the Sigrity environment, but then be able to migrate data into other parts of the system based on that.
The design database is at a neutral. I mean, Cadence has been doing that on the IC side of things for a number of years, with open access, right? We strongly feel that we can get some of the same advantages with IPC-2581.
10:36 Do you think that IPC-2581 has a strong future?
Yes, very much so. I think the future is very bright for IPC-2581.
From the internal activity I see, and not only in the analysis tools making sure we can support translating from that format into our analysis tools, I can tell you, we’re heavily invested and we wouldn’t be heavily invested if we didn’t see that there wasn’t a future there.
10:58 What is the support Cadence provides for a specific device design layout?
Alright so if we are talking about standards and interface standards in particular whether they’re DDR-4 or whatever. We’ve had some initiatives in the past on interface based design. At the current time they are more suited to the front end environment, the logic environment, where you can better manage those interfaces. I know we have an extensive suite of compliance kits from major interfaces for the analysis side of things. I think there might be a little bit of a void, if you will within in Allegro, or from the layout applications but we seem to have it covered from a front end. We’ll probably be doing some things in the future from a constraint perspective around those, though.
11:48 How do you think tools will evolve in the future?
Well one of the things that I can talk about, not to say I have my own crystal ball, but a road map in terms of where we’re headed. One thing I see is that there is a lot of move with a lot of EDA companies to do concurrent design. And that concurrent design seems to be focused just at the layout level, taking as many layout people as you can, working on a design concurrently. We see a tremendous opportunity there to maybe plug in analysis to that as well.
Why would someone want to be working on a design that is rapidly changing and then have to take off a static version of that design and send it to someone else to be analyzed? By the time the data comes back and someone wants to take a look at or fix it, the designs way ahead of where it would have been if just one person was working on it.
So, something that we see that there’s a potential to do in the future is for the signal integrity or power integrity expert to be able to plug into that concurrent design. Someone, maybe the layout designer generated some type of report coupling whatever and had a question. Well why wait to get an answer? Have them plug into the session and show them and then they can quarry things on the board. Or an signal integrity or power integrity expert can jump in lock down a section, do some analysis, now that collaboration issue of getting the data that needs to be fixed to someone else can almost happen in real time.
13:04 What do you call this? Concurrent design?
Concurrent design from an internal or product feature name, as far as Allegro concerned, it’s called Symphony.
We’ve always felt very strongly about the entire design flow. How the players in that flow are able to communicate with one another, share design data, get their designs out quicker, etc.