How to Route a PCB in KiCad

by | Jul 7, 2020 | 0 comments

In this tutorial, we will show you how to execute PCB routing in KiCad. Let us go through the PCB stack-up before we get to the PCB routing.

Arranging stack-up in KiCad

We selected an 8-mil track width and spacing for the differential pair. But this needs to be done in a proper way, according to the stack-up that contains certain requirements like impedance, number of layers, thickness of the PCB, etc. Depending on the requirements you can generate a stack-up. 

You can see in this stack-up a 90-ohm impedance on the top layer 1 and layer 4 (signal layers). The outer dark green layers in the stack-up are the top and bottom solder mask. The yellow layer represents the core and the light green layer the prepreg.

Stackup Planner by Sierra Circuits

The 0.5 oz copper foil comes with a 0.5 oz plating, so in total it will be 1 oz. These outer layers are 1 oz and the required finished thickness is 62 mils. This is the total thickness of the board. And this is the estimated thickness of the lamination. So, this has a tolerance of +/- 6.2. The top and bottom layers have a 90 ohm impedance and a differential line width of 5 mils. You can see that the finished line width is 5 mils for layer 1 and layer 4 and the finish spacing is 4 mils.

Sierra Circuits stackup and impedance report

Sierra Circuits stack-up and impedance report

The differential pair width should be 5 mils and the spacing between the two tracks should be 4 mils. See how to route differential pairs in KiCad.

KiCad critical routing 

We will start what we could call the critical routing. 

KiCad Critical Routing

KiCad critical routing

We want a plane on layer 3 which is a power plane and we want a plane of net VCC

  To draw a plane: 

  • Select Add Filled Zones button on the vertical toolbar
  • Click from where you want it to start.
  • Select Power plane “POWER.Cu_ 
  • Select a chamfer of 5 mils
  • Choose Pad connections as “Solid”
  • Click Ok
KiCad Copper Zone Properties

Specifying a plane

We are drawing a plane in the left bottom side because the VCC is present in this section. We have to define +5V for the remaining area on the third layer. The planes are now set up for VCC and +5V.

KiCad Drawing a Plane

Drawing a plane on circuit layout

Let’s route the main tracks, which are power tracks of 9V over here and +5V that runs along this line to this point. This is the VCC point coming from the connector towards this point and this one is the VCC running into the circuit. 

KiCad Add Filled Zones

Add filled zones

Select Add Filled Zones again, draw a complete plane on the layer because this is just a 9V and it will be running only in this region. You don’t have to draw a special plane on layer 3, you can directly draw it on layer 1.

KiCad Drawing a Plane for +9V

Drawing a plane for +9V

We are drawing a plane in this region because this is a power plane and it will carry high current. Similarly, we need to draw a plane for this +5V. 

FB1 and C13 connected with through-holes

FB1 and C13 connected with through-holes

As shown in the image above there is a connection between FB1 (ferrite bead) and C13 (capacitor) but you can’t see any line over here as we have created a plane on layer 3 and this is a through-hole component. Through-hole components normally connect to all the layers. Since there is a plane on layer 3, FB1 and C13 are connected through layer 3. The C13 through-hole that is going through layer 3 is connecting to FB1. It is always a good idea to have a plane because it improves the flow of the current.

Crystal Routing

A crystal is basically a continuously varying signal which is required for any microcontroller to operate and used as a reference signal. This should be very close to the microcontroller and its track should be as short as possible. 

KiCad Crystal Location

Crystal location

We will route this line. Select on the right hand side Route Tracks and mention 10 mils. You can go with 10 mils when the board is not congested. If it is congested, then you can reduce to 8 mils. Depending on your requirements, you can even reduce to 6 mils.

First, let’s do the routing of the critical nets. As mentioned earlier, the crystal routing has to be as short as possible. 

Setting up Connection to Ground

Grounding capacitor through via

The ground of a crystal should always be connected to the nearest ground pin. C4 can be connected to a ground pin as shown in the image above. Now, the via is placed and will connect to the ground plane through the ground pins. 

To connect C3 to the ground plane, you can place a via to connect to the ground as shown in the image above. In some high-speed designs, you can follow guard ring technique.

To place a via:

  • Type V on your keyboard
  • Click on the board to place the via
  • Choose Cancel. 

Routing for decoupling capacitors

First, we need to deal with the decoupling capacitors. You can see these are decoupling capacitors

Decoupling capacitors

Decoupling capacitors

Here, the +5V comes from the regulator. And the track from the regulator should go towards C5 pins through the capacitor, not directly through the 5V. Let’s connect this top layer and have the 5V distributed through it. We can place a via near C5. Now, the +5V will come through the plane towards the C5 capacitor through the via, and then it will go to the power plane.

KiCad Via to route +5V

Via to route +5V

As shown in the image below there is a power plane, VCC, and this is a capacitor. Select Route Tracks and connect this over here. So this plane is connected but the VCC is still not connected and we have placed a plane on the layer. So we will take this one again and connect this, click V and place it. Now Cancel and OK.

KiCad Via to Route through VCC Plane

Via to route through VCC plane

Now, the connection will come through the VCC plane, go through the capacitor, and go to VCC. Every decoupling capacitor should be routed this way. 

KiCad main pin routing

The next step is to deal with the main pins. These are the control lines with which we can control operations. They will also give information about whether the data is available on the chip or not. 

KiCad Main Pins before routing connections

Main pins before routing connections

These pins are connected here to these connectors. Normally, we follow an orthogonal entry rule while routing on top and bottom layers. An orthogonal entry means that the top lines are at 90 degrees with respect to the bottom lines. Select the top layer, select this line and take a line from here.

KiCad Main Pins after routing connections

Main pins after routing connections

These are my 8 data lines that are going to the IC and these pins should be connected to this connector.

We actually need to move one of the tracks slightly away from the crystal zone. The data lines are connected and we need to connect these lines to this connector. Use the bottom layer, select the line and select bottom.

You can see these lines are running horizontally. But the top to bottom line is running vertically. This makes the PCB routing very easy if you’re routing different lengths on the top and bottom. 

We can connect the via to these tracks on the top. Over here, slightly to the left. You can take this track straight up and put a via over here.

Routing the top and bottom layers

We are demonstrating the principle of PCB routing horizontally and vertically on different layers. This is the top layer.

KiCad Top Layer

PCB top layer

And this is the bottom layer.

KiCad PCB Bottom Layer

PCB bottom layer

We will now show you how to do the entire PCB routing. Let’s go ahead and save this part first and close it. 

KiCad Saving the first part

Saving the first part

As you can see, this is a completed PCB routing. You can see the planes. We have used a complete plane over here which is connected through layer 3. If you want you could also have a plane over here on top. You can see this via over here that is coming from the plane through the capacitor and the pin. Same scenario over here.

Now, let’s have a look at the bottom lines. Here, they are in green.

KiCad Bottom Layers designated in Green

Bottom layers designated in green

Once the PCB routing is completed, the next step is to make sure that the designators don’t overlap with the pairs. It’s fine if they overlap with the tracks but not the pairs.

You can see at the bottom, there is a designator. And similarly over here.

Ref text placement

It is possible to place your ref text over your vias, if they are tented, which means they will be covered with solder mask. But it is always a good practice to keep your ref text away from the pads as well as the vias. If it is not possible to keep it away from your vias, then tent your vias.

To move the ref text, place the cursor on it, select it and find a suitable place. If you place it over here, you can see that this line is the switch assembly line, so it will be covered on the assembly line. You need to select a proper place and make sure that the distance from the ref text is at least 6 mils from the pads.

Right now, the ref text sizes are quite big. To change the size, go to Edit and Edit Text & Graphic Properties. Select the footprint references and select the layer. Here, the line thickness is 6 mils and the text width and height will be 30. The text thickness is also 6. 

Edit Text and Graphic Properties Dialog Box

Edit text and graphic properties dialog box

Now that the size is reduced, it is easier to do the placement. If you zoom in a bit, you will see a white line on the footprints. If you can see this footprint on the right-hand side, this is nothing but a place bound. It is always a good idea to keep the ref text outside of this place bound so there is no possibility of interfering with the actual pads.

KiCad Ref Text Placement

Ref text C11 placed cleanly outside bounds (white lines)

KiCad design rules checker (DRC)

Let’s complete the entire placing of the ref text before starting with the DRC checks. Make sure that all the ref texts are away from the pins. Once this is done, you need to start with the DRC checks, which are the rules that have been set up at the beginning. This will check whether those rules are being followed or not. So let’s see how it works. Save this and go to Inspect and Design Rules Checker. This is the minimum track width as per the DRC. 

To create a report file:

  • Click Inspect and select Design Rules Checker
Inspect Menu Design Rule Checker

Inspect Menu > Design Rule Checker

  • Select Refill all zones before performing DRC
  • Select Create report file
  • Click Run DRC
Creating Report File

Creating report file

  • Specify the report file location and click Save
KiCad Saving Report File

Saving report file

Now the DRC tells us there are a few errors. Most of these errors will concern the differential lines. For instance, here it says ‘two track ends too close.’ Right now, we don’t have to worry about this because we have set a particular rule for the minimum distance between two tracks.

KiCad DRC Error Report

DRC Error Report

All the errors are in the section shown in the image below and are all the known errors. Even if we knew this would happen, it is possible to avoid it. We can change the clearance to 10 mils and the spacing to 8 mils. The DRC is considering each track separately and since the spacing is just 8 mils, it is actually not following the rule of 10 mils. That’s why it is indicating there is an error, which can be ignored.

KiCad Track Clearance error

Track clearance error

If there are any other errors in the DRC, you need to solve them before going further.

This is how we carry out PCB routing in KiCad.

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