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Learning about High-Speed PCB Design

Author Profile img: Amit Bahl

By Amit Bahl

February 20, 2014 | 0 Comments


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Advances in semiconductor manufacturing have paced the development of electronics for six decades. The smallest transistor geometries are one thousandth the size possible 40 years ago, and that scaling, along with innovations in materials and architecture, has resulted not only in the integration of whole systems on chips, but device speeds that now challenge the limits of carrying digital signals over copper traces on FR-4 for distances as long as a desktop computer motherboard.

Low-loss Laminates on the Horizon

I venture that progress in electronics now hinges not so much on semiconductor advances as it does on a transition to PCB laminates that have better dielectric properties than FR-4. Consider the latest USB chip sets. A consortium of semiconductor, PC, and software companies drafted the original Universal Serial Bus standard in the 1990s to provide a common interface for connecting all sorts of peripherals to personal computers, one that could support the disk-drive data rates at the time and also supply power to external equipment. That standard specified two communication modes: a “full-speed” mode with a 12-Mb/s maximum signaling rate and a low-speed mode for such devices as a keyboard or joystick. The USB topology consists of a central host residing in a PC, and multiple ports downstream of that host controller, which can connect with peripherals that may in turn serve as hubs for communication with other equipment.


Eventually, the expense of developing tricks to skirt the limitations of conventional PCB materials won’t be cost-effective, and the slight premium for a material with far less loss will be well worth the price.




The original standard was amended within a few years by USB 2.0, which upped the maximum signaling rate by 40 times to 480 Mb/s. That version was superseded in 2008 by USB 3.0, which increased the maximum rate to 5 Gb/s. USB 3.0 is backward-compatible with the preceding standard, but includes a new high-speed bus in parallel with the USB 2.0 bus. In 2013, the standard was again upgraded, adding an even faster transfer mode whose ceiling is 10 Gb/s. The first chip sets to support the latest version of the standard, USB 3.1, will be introduced this year.

Also read, What Is PCIe (PCI Express)?

Compensation Has Limits

A peripheral that would communicate in the fastest mode can be connected to the host by a cable up to a meter long. The total allowable loss in the channel end-to-end through the external device to the host controller is -20 dB at the maximum signaling rate, according to the model by the USB organization. The channel model includes loss from the cable, loss from the connectors, loss in the device PCB, and at most a 7-dB loss across the host PCB, based on a 10-inch maximum trace length there. Active repeaters would be required if loss exceeds that 7-dB budget. Of course, the rescue to compensate for the signal degradation through the channel is equalization, both on the transmit and receive sides.

Microchip, one of the companies that manufactures chip sets to implement USB 3.0 (5-Gb/s maximum signaling rate), points out in their implementation guidelines:

Signal losses for copper traces running on FR-4 materials can be very significant at USB 3.0 SuperSpeed (SS) signaling rates. Ways to mitigate losses include:

  1. Keep SS traces as short as practical. This is the single most practical and cost-effective thing that can be done to reduce signal loss.
  2. Route SS traces on outer layers, rather than on inner layers.
  3. Consider laminates with lower DF and DK ratings. These lower-loss materials include FR408HR, FR408HRIS, N4000-13SI, Rogers.
  4. Try to route SS signals at a 45-degree angle to the material weave direction so that the trace does not occasionally line up with a high-resin, high-loss path.
  5. Consider low-loss materials, like N4000- 13SI or Rogers.”

Note they twice emphasize switching from FR-4 to low-loss materials and this is in an application note for devices to implement 5-Gb/s communication, not the upcoming chips to enable double that rate.




USB Compliance Testing

Jim Choate, the USB technology product manager at Agilent Technologies, recently presented a webinar about compliance testing for USB 3.1 devices. He started his career working on computer motherboard design and validation at Intel during the 1990s and later served as the USB Implementers’ Forum (USB-IF) compliance committee chairman. He contends there is enough margin to push USB signal rates beyond 10 Gb/s without abandoning FR-4 for PC motherboards, but concedes repeaters would be necessary and very likely much different architectural approaches for USB chip sets. From his experience at Intel, he believes that using a material other than FR-4 for a PC motherboard would be a deal-breaker.

Who would wager that each future generation of semiconductor devices, whatever their function, won’t be faster than their predecessors? Eventually, the expense of developing tricks to skirt the limitations of conventional PCB materials won’t be cost-effective, and the slight premium for a material with far less loss will be well worth the price. I submit that we’re close to that threshold.

There’s nothing intrinsically expensive about the constituents and manufacture of many high-performance materials, except for the special SiO2 glass in some products. Naturally, while the demand for such materials is low, their price will remain a little higher than that of materials in high demand. If you are interested to know more about high-speed designs, check out our case study on high-speed video board.

Would 30% lower loss at 10 GHz be worth it to you? Let us know in the comments below.



High-Speed PCB Design Guide - Cover Image

High-Speed PCB Design Guide

8 Chapters - 115 Pages - 150 Minute Read
What's Inside:
  • Explanations of signal integrity issues
  • Understanding transmission lines and controlled impedance
  • Selection process of high-speed PCB materials
  • High-speed layout guidelines
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