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Sierra Circuits manufactured and assembled a two-board PCB system designed using Quilter AI. The project, called Speedrun, consists of a system-on-module (SOM) and a baseboard built around the NXP i.MX 8M Mini processor.
Since the layouts were generated rapidly using automation, our team performed DFM, DFA, and CAM reviews to align the design with class 2 standards.
In this case study, you’ll learn how our experts refined trace geometries, via structures, and component footprints to ensure manufacturability.
As a PCB designer, understanding these considerations helps you reduce unnecessary back-and-forth communication and shorten turnaround time.
Highlights:
To ensure manufacturability, our engineers:
- Performed DFM, DFA, and impedance validation to verify the manufacturability of the AI-generated layouts.
- Refined CAM data, including stack-up adjustments, to improve fabrication reliability and process stability.
- Optimized the PCB stack-up thickness and replaced TU-768 with Ventec VT-47.
An overview of the project Speedrun
A single engineer designed a working computer using Quilter’s physics-driven AI in less than a week.
The AI automatically placed components and routed traces, followed by a brief human cleanup phase before manufacturing release.
The design was based on the NXP i.MX 8M Mini Evaluation Kit.
The reference design utilizes the following system-on-module (SOM):
| Category | Specification |
|---|---|
| SOM | 8MMINILPD4-CPU2 |
| Processor | i.MX 8M Mini – Quad AArch64 CPU with integrated GPU/VPU (Linux-ready) |
| Memory | 2GB LPDDR4 |
| Storage | eMMC Flash |
| Connectivity Interfaces | USB, PCIe, HD400 SDHC |
Wi-Fi and Bluetooth modules were not included due to supply chain issues.
The project Speedrun implements an embedded Linux system capable of high-speed memory operation, video streaming, and mixed-signal subsystem support.
The two-board architecture, comprising a system-on-module (SOM) and a baseboard, integrates 843 components and 5,141 pins, along with Ethernet, USB, audio, M.2, and multiple user-interface connectors.
Dual-board system with an SOM and a bareboard (Image credit: Quilter).
Sierra Circuits fabricated and assembled the boards entirely in-house, maintaining class 2 fabrication, assembly, and inspection standards.
Despite the design’s density and complexity, the system powered up successfully on the first attempt.
During DFM and DFA analyses, our engineers focused on:
- Identifying manufacturability risks
- Applying CAM-level modifications wherever feasible
Dual-board system specification
The dual-board architecture consists of two boards with different fabrication requirements.
The system-on-module (SOM) uses an 8-layer HDI stack-up to support dense routing and fine-pitch components. The baseboard features a standard 8-layer construction for cost-effective signal and power distribution.
The specifications below summarize the key design and manufacturing parameters.
| Parameter | Baseboard | System-on-Module (SOM) |
|---|---|---|
| Layer count | 8-layer, derived from NXP i.MX 8M Mini EVK | 8-layer HDI |
| Fabrication class | IPC Class 2 | IPC Class 2 |
| Trace/space | 3.5 mil | 2 mil |
| Component count | 500 | 843 |
| Total pin count | 2000 | 5141 |
| Interfaces | Ethernet, USB-C & OTG, audio, M.2, Mini-SAS, Hirose HSMC, and IO headers | i.MX 8M mini, LPDDR4, and eMMC |
How Sierra Circuits refined the layout for class 2 manufacturing
To ensure the AI-generated layout is aligned with IPC class 2 standards, our team applied a few refinements. Each update was carefully reviewed to preserve the original design intent.
The sections below outline the improvements in detail.
1. Aligned the stack-up thickness with the manufacturing standards
The fabrication notes specified a 47-mil finished thickness, which did not account for copper plating, surface finish, and solder mask. To ensure fabrication compliance, the expected finished thickness was adjusted to approximately 50 mil (±10%).
Quilter’s fabrication notes were originally derived from the NXP reference design, which specified TU-768 material. However, Sierra Circuits recommended the use of Ventec VT-47 material, requiring the fabrication notes to be updated accordingly.
This variance was reviewed with the Quilter team, and the final thickness was confirmed and approved before fabrication.
2. Optimized copper weight to match trace geometry
Our experts identified that the specified inner-layer trace width and spacing of 3 mil were not suitable for the selected 1 oz copper weight. It requires a minimum of 4 mil line width and 4.25 mil spacing.
To ensure manufacturability, our DFM engineers modified the copper weight on inner layers to 0.5 oz.
The updated configuration was reviewed and approved by the Quilter team.
3. Eliminated an outer-layer trace stub
CAM review identified an unterminated trace stub on the top layer. This dangling copper segment was not connected to any active net and created an impedance discontinuity.
This issue originated when the NXP baseboard reference design was translated from Cadence Allegro to Altium Designer. Allegro used actual trace segments for thermal spokes, which remained as leftover objects after importing into Altium Designer.
The stub could cause signal reflections, degrade signal integrity, and impact high-speed performance.
Our DFM engineer removed the unused trace segment with Quilter’s approval. Eliminating the stub restored a clean signal path and minimized the risk of signal integrity issues.
4. Added solder mask openings to vias
DFA checks revealed that several vias did not have solder mask openings.
The issue originated from a newly downloaded USB-C footprint from GCT, where the Altium version exported from Ultra Librarian did not include solder mask openings.
Without proper mask clearance, these locations could be partially covered during fabrication, leading to poor solderability, assembly defects, or unreliable electrical connections.
Missing solder mask opening on the marked holes.
Our engineers added solder mask openings to the affected locations. A 1:1 ratio between the solder mask opening and the underlying pad was maintained to ensure proper alignment and consistent assembly results.
5. Refined component footprints and assembly details
DFA checks showed that several components had incorrect or incomplete footprints, which could lead to assembly defects and rework. The issues included:
- Mismatch between the Gerber files and the datasheet-recommended footprints/ This can lead to pad extension beyond the land pattern.
- Pin number discrepancies between the datasheet and the silkscreen layer.
Our engineering team requested the latest component dimensions from the Quilter team. The footprint was updated to match the manufacturer’s datasheet.
After reviewing the datasheet, we also corrected the footprint and marked the correct pad as pin 1 for the affected components.
The Speedrun project demonstrates how AI-driven PCB design and manufacturing expertise can work together to accelerate complex system development.
Quilter’s AI-enabled rapid layout generation and Sierra Circuits’ DFM, DFA, and CAM teams ensured the design aligned with the IPC class 2 standards.
Close collaboration between the two teams enabled informed engineering decisions without unnecessary redesign cycles.
Despite tight tolerances, dense via structures, and advanced routing requirements, the dual-board system was successfully fabricated and assembled in-house and powered up on the first build. The project highlights the value of combining AI-based EDA tools with experienced manufacturing validation.
About Pooja Mitra : Pooja Mitra is an electronics and communication engineer. With an experience of over three years in the PCB industry, she creates industry-focused articles that help electrical and PCB layout engineers.
