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Ultra-HDI PCB Manufacturing Using mSAP Technology

Sierra Circuits manufactures 2/2 mil line and space features with precise trace geometry and tight impedance tolerances.

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How are Ultra-HDI Boards Manufactured?

  • UHDI designs use the mSAP process to create ultra-fine 2/2 mil traces and spaces that are difficult to achieve with conventional subtractive etching.
  • The process produces highly defined copper features with near-vertical sidewalls and minimal undercut, helping maintain consistent impedance and signal performance.
  • The resulting traces are smoother and uniform, reducing insertion loss and signal degradation, much needed in high-speed designs.
  • Thinner traces and tighter spacing also create more room for component pads, microvias, and other critical features, increasing circuit density without adding layers or increasing board size.
Ideal for:
  • Compact and high-density designs
  • Fine-pitch component routing
  • Tight impedance requirements
  • Dense RF and microwave layouts
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Advanced UHDI Manufacturing Capabilities

  • At Sierra Circuits, we have been perfecting our ultra-HDI process since 2014 to consistently manufacture 2/2 mil (50/50 µm) trace-and-space features.
  • We utilize SmartLam Dynachem laminator for uniform dry-film application and Nuvogo laser direct imaging (LDI) system for high-resolution patterning and superior registration accuracy.
  • We accurately control photoresist exposure, curing, and electroless copper deposition to produce fully defined trace sidewalls and maintain critical feature integrity.
  • We employ advanced plating and filling processes for laser-drilled microvias and stacked vias to create reliable interconnections in high-density designs.
  • Our engineering team provides DFM analysis, stack-up optimization, and material selection recommendations tailored to your ultra-HDI and mSAP designs.
Stack-Up Stack-Up
Supported PCB Types   Rigid PCBs only (no flex)
Maximum Layer Count16
Maximum Layers with 2/2 TechnologyUp to 4 layers in the stack-up may utilize 2/2 technology
Maximum Copper Plating Thickness25 µm (1 mil) on layers containing 2/2 mil features
Maximum Overplating Tolerance±2 µm (0.079 mil)
Plating Uniformity Across the Panel±10%
LDI Registration Tolerance ≤±12 µm (0.472 mil)
Supported MaterialsFR-4, Tachyon 100G, Panasonic Megtron 6, EM-528, and EM-892K
Unsupported MaterialsRogers
Maximum Board Size6"×6"
Trace and Space Clearance Trace and Space Clearance
Minimum Trace/Space   50/50 µm (2/2 mil)
Copper Thickness8–12 µm (0.31–0.47 mil)
Resist Thickness30 µm (1.18 mil) DI 9530 Dupont Dry Film
Plating Overgrowth Allowance+5–8 µm (0.20–0.31 mil) per side
Artwork Compensation−6 to −10 µm (−0.24 to −0.39 mil)
Minimum Trace-to-Via Pad≥60 µm (2.36 mil)
Minimum Trace-to-Copper Pour≥50 µm (1.97 mil)
Minimum Trace-to-Soldermask≥75 µm (2.95 mil)
Drill Parameters Drill Parameters
Via FillNot supported on outer layers containing 2/2 mil features
Laser Via Plating ThicknessUp to 20 µm (0.8 mil)
Laser Via Diameter75–100 µm (2.95–3.94 mil)
Capture Pad100–125 µm (3.94–4.92 mil)
Minimum Annular Ring (IPC Class 2)25 µm (1 mil)
Minimum Mechanical Drill Size
    104 µm (4.1 mil) for 2-layer boards ≤32 mil finished thickness
    150 µm (5.9 mil) for boards with ≥2 layers
Surface Finish Surface Finish
Surface Finish Available
    If the 2/2 mil line/space features are not covered by the solder mask, only the immersion silver surface finish is allowed.
    If the copper feature is covered by solder mask, any standard surface finish may be used, including HASL (vertical), Lead-Free HASL, OSP, ENIG, Electrolytic Soft Gold, Electrolytic Hard Gold, and Selective Gold.
    Lead Time Lead Time
    Typical Lead Time1 week per lamination cycle
      Note: Actual lead times may vary based on design complexity, including stacked laser vias, via-in-pad, edge-plated slots, and laser-milled cavities.
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    DFM Guidelines for Ultra-High Density Interconnect PCBs

    • For multilayer designs, place 2/2 mil trace and space features only on the outer stack-up layers. Avoid routing ultra-fine features within thick core layers or buried structures.
    • Avoid placing stacked microvias directly within 2/2 mil routing regions.
    • Maintain balanced copper distribution throughout fine-line regions and avoid large copper voids to improve manufacturability and plating uniformity.
    • Keep 2/2 mil circuitry away from panel edges to reduce the risk of fabrication defects and improve manufacturing yield.
    • Consider the increased resistance of ultra-fine traces when routing long signal paths. For example, a 50 µm-wide, 10 µm-thick copper trace has an approximate resistance of 0.5-0.6 Ω/in.
    • Reserve 2/2 mil traces for signal routing and avoid using them for power distribution.
    • For high-speed RF, SerDes, and impedance-controlled designs, account for trace geometry, copper characteristics, and material properties during signal integrity analysis.

    How to place an order for your UHDI PCBs

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    Trusted by innovators

    Engineers at the worlds most innovative companies choose Sierra Circuits for the highest quality ultra-HDI bord fabrication and assembly, right here in the USA.

    Sierra Circuits is
    headquartered in Silicon Valley.
    We welcome visitors at
    our 70,000 sqft facility,
    located at 1108 West Evelyn Avenue
    in Sunnyvale, California.
    Book a tour with an account manager today!
    Let us introduce you to one of the most innovative communities of engineers and designers in the world.
    We can help you plan your project from design to assembled board.

    Manufacturing Equipment at Sierra Circuits

    Our 70,000 sqft state-of-the-art campus in the heart of Silicon Valley contains the most advanced equipment required for the manufacture and assembly of your PCBs. Whether you’re looking for standard quick turn PCBs or boards with the tightest tolerances, made from exotic metals, there’s a reason Sierra Circuits leads the industry in quality and performance.

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