Z-Zero’s Stack-Up Tool for Digital Hardware Engineers to Collaborate With Manufacturers

During DesignCon 2018, we met Bill Hargin, “Director of Everything” at Z-Zero, an innovative PCB stack-up design company. Bill told us about Z-Zero’s stack-up tool and shared some precious tips for PCB designers.

0:08 Tell us about your company and the products you provide.

The company is called Z-Zero, our software is called Z-Planner, and it is designed to be a collaborative environment between digital hardware engineers primarily, and people that would do signal integrity analysis and board design, to collaborate with laminate manufacturers, and also fabricators like yourself.

0:37 Can you give us some insight on your stack-up tool?

Ever since leaving Mentor Graphics, I have been working on a stack-up design tool that would marry the fabrication part of the world with the signal integrity part of the world, and put them together in one software package.

0:58 Does it still use the HyperLynx base chip for calculations?

Yes, exactly. It uses the HyperLynx field solver.

1:05 Is it 2D or 3D?

It’s a 2D field solver, but for planes and signals and dielectrics, that is fine. You do not need 3D, unless you are looking at vias. I would leave vias to the other simulators.

1:20 What are the features that you can take care of from the PCB manufacturers or PCB material characteristics’ database?

I think there are a few things that engineers struggle with, as it relates to materials and stack-up design. Actually, a lot of things, they struggle with. One of them is Dk and Df as a function of frequency. What Dk, what dielectric constant do I need to use in my stack-up design for my impedance calculations? Do I get it from a data sheet? Is it the right value? Is it based on the right resin content? If I am not tracking resin content, how do I know that my Dk and Df are correct? If I am not tracking frequency, how do I know it is correct? My software handles all of that explicitly, and in great detail.

2:12 How does your software collect all the data?

Most, if not all of the laminate manufacturers, capture that data in their labs and produce what I refer to as Dk and Df tables. Constructions, thicknesses, resin contents and Dk and Df as a function of frequency. I take all that data, and I also collect things like water absorption, Poisson’s ratio, Young’s modulus, CTE numbers, and I put that all into my library. I have over 60 materials today, characterized in the library, times all the cores and all the prepregs offered by most of the high speed laminate manufacturers. That is all in the library. One stop shopping. You can visualize the database. You can filter the database on Dk, Df, decomposition temperature, CTE. Anything you can think of that relates to materials, the database can be filtered on those, and you can pop up graphs. It kind of works like Excel, but it is tuned to this specific problem.

3:35 Are you using the stack-up tool for modeling and controlling business faces?

The stack-up tool allows you to define the cross-section, including copper roughness…

3:48 For loss calculations?

Yes, for loss calculations. My tool would look at total loss, conductor loss, skin effect, copper roughness loss, dielectric loss. At any frequency, it would break those different lost components into their pieces. Like of my total loss, how much is from the copper? I would show that to the user. The other thing that a lot of people, a lot of engineers, I find struggle with, and even some fabricators, which is surprising to me. Engineers struggle sometimes with knowing finished prepreg thicknesses. They know what the sheet thicknesses are, maybe, if they have done some homework, but how does it press out? My software calculates that.

4:41 Do you enter the copper percentages?

There are three different options for that. You could either pull it out of the CAD tool, put in the copper percentage, or make some assumptions like signal layers are 50%, that kind of thing. The engineer can use that to send that data to their signal integrity tool. When they send it to the SI tool, then the thousands of simulations they do for signal integrity are now based on an accurate representation of the stack-up. I called the stack-up, The Foundation of Signal Integrity. If the foundation is bad, the structure above it is questionable.

5:26 Do you have any resources to help PCB designers?

I should probably throw out something that might help some of your customers, or potentially mutual customers. I have got a stack-up design tutorial on Z-Zero.com. If you go to Z-Zero.com, you can download the evaluation software. It has a two and a half hour tutorial that takes you through actually designing a stack-up with the real material, and doing impedance and loss planning. Very educational.

6:03 Is your tool easy to interface?

I’m looking to add more from some of the other signal integrity tools, but right now, I import and export from HyperLynx and also IPC-2581. Anybody who can handle IPC-2581 stack-up data – Cadence can handle that, several tools can.

6:34 Is it bidirectional?

Yes, it is bidirectional. And I’m adding additional interfaces based on customer demand to other signal integrity environments. Possibly ODB++.

6:51 Can you tell us about your presentation?

One of the things I am presenting on tomorrow at this event is, I am hosting a panel discussion called How To Avoid Getting Totally Skewed. It is about glass weave skew. Over the last few years, I have kind of become a semi-authority on glass weave skew. Understanding why it happens, how to present it. In fact, Dr. Eric Bogatin and I, and some of his students, got a Best Paper Award given to us last year for some glass weave skew research. We are presenting it tomorrow. I will probably be doing some webinars on glass weave skew as well, if you guys want to jointly promote them to our customers, that might be interesting.

7:50 Are there any design practices you would advise to PCB designers?

There’s a lot of things you can do. The most basic one is to realize at what frequency you need to start worrying about it. I would say five gigabytes per second and above, roughly two and half gigahertz, you need to start worrying about it, and looking at what your skewed tolerance is for those interfaces. The CAD package can handle length, most of the IP providers can make sure a differential signal is symmetrical coming out of the BGA, but the skew thing has kind of a random component. You do not know when it is going to happen. To prepare for it, some people rotate their artwork. I do not know if you have done that for some of your customers. Some people zigzag their traces 10 degrees. That is one of the fixes. Another thing is to become savvy to the different glass weave styles. Some of them are better than others. Spread glass is a good tool. Matching your differential pitch to your glass pitch can be a good approach. Then you have a symmetrical microenvironment around your differential pair. Those are just some of the techniques that can be used. We will be talking about all of those in the panel session tomorrow.

“If you are waiting to get the proper stack-up design and material selection to the point in your process where the fabricator is getting ready to build the board, you are way too late.”

9:35 Are there any other tips you could give to PCB designers?

I think I would say this: If you are waiting to get the proper stack-up design and material selection to the point in your process where the fabricator is getting ready to build the board, you are way too late. That entire decision process needs to happen before you simulate most of your signals. You have got to lock in the stack-up first, then do you your simulations. Every transmission line that you simulate with a signal integrity tool is dependent upon the stack-up. Trace width, dielectric thickness, dielectric constant at frequency, resin content, and so on. You need to nail that down before you do all your simulations, otherwise they become invalid. If you do not get one parameter right in a cross section, you have invalidated the entire cross section. It is not like it is partially right and therefore okay. It is 100% wrong.

If you get one parameter wrong, your impedances are wrong. Your trace widths are wrong, your dielectric thicknesses are wrong, your Dks and Dfs… What if I think that the dielectric material is four mils and the trace width is five mils, and when I get to you in the fabrication process, you say, “No, I want it to be 4.3-mil wide” and the dielectric thickens is actually going to be 4.15 or something like that? Now, all of the simulations are based on the wrong assumptions. The Dk may be wrong. My loss budget, now I have widened the trace, well that could help, what if you narrowed the trace?

Now your skin effect goes up. My loss profile has changed. If I was near the edge, I could have violated my loss budget, shrinking my I-patterns. I say, why not get it right at the beginning of the process? Then by the time your fabricator gets involved, you have already done the engineering. You are an electrical engineer. Do your homework.

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