Optimizing Power for Clocks and other Sensitive Applications

Introduction

The topic of clock jitter performance seems to be a current focus of clock, ADC, and power supply manufacturers.  The reasoning is clear; clock jitter interferes with the performance of digital circuits including high speed ADCs.  High speed clocks can be quite sensitive to the “cleanliness” of the power they receive, though quantifying the relationship takes some effort.

Continue reading “Optimizing Power for Clocks and other Sensitive Applications”