On May 17 and 18, Sierra hosted a workshop on PCB Layout Design Engineering. Whether you attended the two-day training or not, check your knowledge on this subject!
#1. Which reference plane did Robert advise you to use to reference controlled impedance traces?
A solid ground plane.
A power plane.
It doesn't matter.
#2. What advice did Robert give about DDR2/3 layout?
Fully route the tracks all at once.
Route all signals of one group by the same topology.
Don't worry about the position of the memory chips.
#3. When it comes to DDR3, what can you do during the pin swapping?
Leave a big gap between the tracks and then swap and connect.
Leave a small gap between the tracks and then swap and connect.
Connect the closest and longest signals together.
#4. In the length matching process, when do you have to do the fine tuning?
At the beginning of the design.
During the preliminary memory layout.
At the end of the design.
#5. What are T-points?
A technique of via stitching.
Virtual points used to length match branches of signals.
A tool to remove unused pad shapes.
#6. When you do a differential pair routing, what should your waves look like?
#7. When it is not specified, what is the distance Robert recommends to length match high-speed signals?
Within 1 mil.
Within 10 mils.
Within 100 mils.
#8. What does Robert advise for the most common high-speed design rules?
Maintain single ended and differential pair impedance.
Keep less space possible between waves.
Route close to the board edge.
#9. What should you do if you need more space in your stack-up?
Remove the top and bottom signal layers.
Add two more power planes.
Add two more signal layers.
#10. Which of the following is not a footprint tip Robert gave?
Make component outline bigger.
Check pin ordering of your footprint.
Never create a BOX around the ribbon cable headers.